Patents by Inventor Xinyun XIE
Xinyun XIE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10957785Abstract: This disclosure relates to the technical field of semiconductors, and discloses a method for manufacturing semiconductor FinFET devices. The method particularly includes pre-removal of a predetermined thickness of a first region of an isolation region on sides of a fin that is not covered by a pseudo gate such that when a layer of second region of the isolation region covered by the pseudo gate is sacrificially removed during a removal of the pseudo gate, the upper surfaces of the remaining first region and the remaining second region of the isolation region are approximately leveled. By using such a method, DC and AC performances of a resulting FinFET device is improved.Type: GrantFiled: June 28, 2019Date of Patent: March 23, 2021Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International CorporationInventor: Xinyun Xie
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Publication number: 20190326418Abstract: This disclosure relates to the technical field of semiconductors, and discloses a method for manufacturing semiconductor FinFET devices. The method particularly includes pre-removal of a predetermined thickness of a first region of an isolation region on sides of a fin that is not covered by a pseudo gate such that when a layer of second region of the isolation region covered by the pseudo gate is sacrificially removed during a removal of the pseudo gate, the upper surfaces of the remaining first region and the remaining second region of the isolation region are approximately leveled. By using such a method, DC and AC performances of a resulting FinFET device is improved.Type: ApplicationFiled: June 28, 2019Publication date: October 24, 2019Applicants: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventor: Xinyun XIE
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Patent number: 10381464Abstract: This disclosure relates to the technical field of semiconductors, and discloses a method for manufacturing semiconductor FinFET devices. The method particularly includes pre-removal of a predetermined thickness of a first region of an isolation region on sides of a fin that is not covered by a pseudo gate such that when a layer of second region of the isolation region covered by the pseudo gate is sacrificially removed during a removal of the pseudo gate, the upper surfaces of the remaining first region and the remaining second region of the isolation region are approximately leveled. By using such a method, DC and AC performances of a resulting FinFET device is improved.Type: GrantFiled: May 8, 2018Date of Patent: August 13, 2019Assignees: SEMICONDUCTOR MANUFACTURING INTL. (SHANGHAI) Corp., SEMICONDUCTOR MANUFACTURING INTL. (Beijing) Corp.Inventor: Xinyun Xie
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Patent number: 10312333Abstract: Fin-type semiconductor device is provided. The semiconductor device includes: a semiconductor substrate and an insulating layer on sidewalls of the plurality of fins. A plurality of fins is projected on a surface of the semiconductor substrate. The insulating layer is located on the surface of the semiconductor substrate. A surface of the insulating layer is lower than top surfaces of the plurality of fins. A thermal conductivity of the insulating layer is larger than a thermal conductivity of silicon oxide.Type: GrantFiled: February 9, 2018Date of Patent: June 4, 2019Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Xinyun Xie, Ming Zhou
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Patent number: 10290724Abstract: A semiconductor device includes a fin structure of a first semiconductor material on a substrate. The fin structure has a source region, a drain region, and a channel region between the source region and the drain region. The device also has a gate structure overlying the fin structure. The source region includes an inner portion of the first semiconductor material and an outer portion of a second semiconductor material overlying a top surface and side surfaces of the inner portion. The drain region includes an inner portion of the first semiconductor material and an outer portion of the second semiconductor material overlying a top surface and side surfaces of the inner portion.Type: GrantFiled: April 26, 2017Date of Patent: May 14, 2019Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventor: Xinyun Xie
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Publication number: 20180337265Abstract: This disclosure relates to the technical field of semiconductors, and discloses a method for manufacturing semiconductor FinFET devices. The method particularly includes pre-removal of a predetermined thickness of a first region of an isolation region on sides of a fin that is not covered by a pseudo gate such that when a layer of second region of the isolation region covered by the pseudo gate is sacrificially removed during a removal of the pseudo gate, the upper surfaces of the remaining first region and the remaining second region of the isolation region are approximately leveled. By using such a method, DC and AC performances of a resulting FinFET device is improved.Type: ApplicationFiled: May 8, 2018Publication date: November 22, 2018Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventor: Xinyun XIE
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Patent number: 10134761Abstract: The present disclosure provides semiconductor devices, fin field-effect transistors and fabrication methods thereof. An exemplary fin field-effect transistor includes a semiconductor substrate; an insulation layer configured for inhibiting a short channel effect and increasing a heat dissipation efficiency of the fin field-effect transistor formed over the semiconductor substrate; at least one fin formed over the insulation layer; a gate structure crossing over at least one fin and covering top and side surfaces of the fin formed over the semiconductor substrate; and a source formed in the fin at one side of the gate structure and a drain formed in the fin at the other side of the gate structure.Type: GrantFiled: September 18, 2017Date of Patent: November 20, 2018Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Xinyun Xie, Ming Zhou
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Publication number: 20180175151Abstract: Fin-type semiconductor device is provided. The semiconductor device includes: a semiconductor substrate and an insulating layer on sidewalls of the plurality of fins. A plurality of fins is projected on a surface of the semiconductor substrate. The insulating layer is located on the surface of the semiconductor substrate. A surface of the insulating layer is lower than top surfaces of the plurality of fins. A thermal conductivity of the insulating layer is larger than a thermal conductivity of silicon oxide.Type: ApplicationFiled: February 9, 2018Publication date: June 21, 2018Inventors: XINYUN XIE, MING ZHOU
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Patent number: 9985015Abstract: A semiconductor device includes a semiconductor substrate having a core device and an IO device. The core device includes a gate interface layer and a high-k dielectric layer on the gate interface layer. The IO device includes a gate interface layer and a high-k dielectric layer on the gate interface layer. The gate interface layer of the core device and the gate interface layer of the IO device each are doped with fluoride ions.Type: GrantFiled: October 20, 2016Date of Patent: May 29, 2018Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventor: Xinyun Xie
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Patent number: 9923065Abstract: In accordance with various embodiments of the disclosed subject matter, a semiconductor device, and a fabricating method thereof are provided. In some embodiments, the semiconductor device comprises: a semiconductor substrate, wherein a plurality of fins are projected on a surface of the semiconductor substrate; and an insulating layer on side walls of the plurality of fins, wherein the insulating layer is located on the surface of the semiconductor substrate, a surface of the insulating layer is lower than top surfaces of the plurality of fins, and a thermal conductivity of the insulating layer is larger than a thermal conductivity of silicon oxide.Type: GrantFiled: July 18, 2016Date of Patent: March 20, 2018Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Xinyun Xie, Ming Zhou
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Patent number: 9899380Abstract: A method of forming a semiconductor device includes providing a semiconductor substrate. The semiconductor substrate includes fins formed thereon and a patterned hard mask layer formed on a top surface of the fins. The method further includes: forming an isolation material layer covering the semiconductor substrate, the fins, and the patterned hard mask layer; performing planarization of the isolation material layer, stopping at the patterned hard mask layer; and performing oxygen ion implantation to form an oxygen injection region within the fins and the isolation material layer; back-etching the isolation material layer, stopping above the oxygen injection region, to form a remaining portion of the isolation material layer exposing a portion of the fins; and performing thermal annealing to cause a thermal oxidation of a portion of the fins through oxygen ions in the oxygen injection region, thereby forming an oxide layer within the plurality of fins.Type: GrantFiled: January 27, 2016Date of Patent: February 20, 2018Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Xinyun Xie, Ming Zhou
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Publication number: 20180006063Abstract: The present disclosure provides semiconductor devices, fin field-effect transistors and fabrication methods thereof. An exemplary fin field-effect transistor includes a semiconductor substrate; an insulation layer configured for inhibiting a short channel effect and increasing a heat dissipation efficiency of the fin field-effect transistor formed over the semiconductor substrate; at least one fin formed over the insulation layer; a gate structure crossing over at least one fin and covering top and side surfaces of the fin formed over the semiconductor substrate; and a source formed in the fin at one side of the gate structure and a drain formed in the fin at the other side of the gate structure.Type: ApplicationFiled: September 18, 2017Publication date: January 4, 2018Inventors: XINYUN XIE, MING ZHOU
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Patent number: 9799676Abstract: The present disclosure provides semiconductor devices, fin field-effect transistors and fabrication methods thereof. An exemplary fin field-effect transistor includes a semiconductor substrate; an insulation layer configured for inhibiting a short channel effect and increasing a heat dissipation efficiency of the fin field-effect transistor formed over the semiconductor substrate; at least one fin formed over the insulation layer; a gate structure crossing over at least one fin and covering top and side surfaces of the fin formed over the semiconductor substrate; and a source formed in the fin at one side of the gate structure and a drain formed in the fin at the other side of the gate structure.Type: GrantFiled: June 1, 2016Date of Patent: October 24, 2017Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Xinyun Xie, Ming Zhou
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Publication number: 20170229559Abstract: A semiconductor device includes a fin structure of a first semiconductor material on a substrate. The fin structure has a source region, a drain region, and a channel region between the source region and the drain region. The device also has a gate structure overlying the fin structure. The source region includes an inner portion of the first semiconductor material and an outer portion of a second semiconductor material overlying a top surface and side surfaces of the inner portion. The drain region includes an inner portion of the first semiconductor material and an outer portion of the second semiconductor material overlying a top surface and side surfaces of the inner portion.Type: ApplicationFiled: April 26, 2017Publication date: August 10, 2017Inventor: XINYUN XIE
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FinFET device having a material formed on reduced source/drain region and method of forming the same
Patent number: 9673325Abstract: A semiconductor device includes a fin structure of a first semiconductor material on a substrate. The fin structure has a source region, a drain region, and a channel region between the source region and the drain region. The device also has a gate structure overlying the fin structure. The source region includes an inner portion of the first semiconductor material and an outer portion of a second semiconductor material overlying a top surface and side surfaces of the inner portion. The drain region includes an inner portion of the first semiconductor material and an outer portion of the second semiconductor material overlying a top surface and side surfaces of the inner portion.Type: GrantFiled: September 1, 2015Date of Patent: June 6, 2017Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventor: Xinyun Xie -
Patent number: 9634087Abstract: A method is provided for fabricating a FinFET. The method includes providing a semiconductor substrate; forming a hard mask layer on the semiconductor substrate, wherein a position of the hard mask layer may corresponds to a position of subsequently formed fin; forming a doping region in the semiconductor substrate by using the hard mask layer as a mask to perform an anti-punch-through ion implantation process; forming an anti-punch-through region by performing an annealing process onto the doping region, such that impurity ions in the doping region diffuse into the semiconductor substrate under the hard mask layer; and forming a trench by using the hard mask layer as a mask to etch the semiconductor substrate and the doping region, wherein the semiconductor substrates between the adjacent trenches constitutes a fin.Type: GrantFiled: August 17, 2016Date of Patent: April 25, 2017Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventor: Xinyun Xie
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Publication number: 20170040310Abstract: A semiconductor device includes a semiconductor substrate having a core device and an IO device. The core device includes a gate interface layer and a high-k dielectric layer on the gate interface layer. The IO device includes a gate interface layer and a high-k dielectric layer on the gate interface layer.Type: ApplicationFiled: October 20, 2016Publication date: February 9, 2017Inventor: XINYUN XIE
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Publication number: 20170033190Abstract: In accordance with various embodiments of the disclosed subject matter, a semiconductor device, and a fabricating method thereof are provided. In some embodiments, the semiconductor device comprises: a semiconductor substrate, wherein a plurality of fins are projected on a surface of the semiconductor substrate; and an insulating layer on side walls of the plurality of fins, wherein the insulating layer is located on the surface of the semiconductor substrate, a surface of the insulating layer is lower than top surfaces of the plurality of fins, and a thermal conductivity of the insulating layer is larger than a thermal conductivity of silicon oxide.Type: ApplicationFiled: July 18, 2016Publication date: February 2, 2017Inventors: XINYUN XIE, MING ZHOU
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Publication number: 20160351591Abstract: The present disclosure provides semiconductor devices, fin field-effect transistors and fabrication methods thereof. An exemplary fin field-effect transistor includes a semiconductor substrate; an insulation layer configured for inhibiting a short channel effect and increasing a heat dissipation efficiency of the fin field-effect transistor formed over the semiconductor substrate; at least one fin formed over the insulation layer; a gate structure crossing over at least one fin and covering top and side surfaces of the fin formed over the semiconductor substrate; and a source formed in the fin at one side of the gate structure and a drain formed in the fin at the other side of the gate structure.Type: ApplicationFiled: June 1, 2016Publication date: December 1, 2016Inventors: XINYUN XIE, MING ZHOU
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Patent number: 9502403Abstract: A method for fabricating a semiconductor device includes providing a semiconductor substrate, forming on the semiconductor substrate a dummy gate interface layer and a dummy gate of a core device and a gate interface layer and a dummy gate of an IO device, removing the dummy gates of the core and IO devices, removing the dummy gate interface layer of the core device, forming a gate interface layer in the original location of the removed dummy gate interface layer, forming a high-k dielectric layer each on the gate interface layer of the core and IO devices, and submitting the semiconductor substrate to a high-pressure fluorine annealing. The high-pressure fluorine annealing causes the gate interface layer and the high-k dielectric layer of the core and IO devices to be doped with fluoride ions.Type: GrantFiled: January 30, 2014Date of Patent: November 22, 2016Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventor: Xinyun Xie