Abstract: The present disclosure provides a semiconductor fabrication method. The method includes providing a semiconductor substrate having first regions and second regions; providing a first gate structure on a first region of the semiconductor substrate, and a second gate structure on a second region of the semiconductor substrate; and forming first trenches in the first region at both sides of the first gate structure. The method further includes forming a first stress layer in the first trenches and a first bumping stress layer on the first stress layer; forming second trenches in a second region at both sides of the second gate structure; and forming a second stress layer in the second trenches and a second bumping stress layer on the second stress layer.

Abstract: A method of forming a semiconductor device includes providing a semiconductor substrate. The semiconductor substrate includes fins formed thereon and a patterned hard mask layer formed on a top surface of the fins. The method further includes: forming an isolation material layer covering the semiconductor substrate, the fins, and the patterned hard mask layer; performing planarization of the isolation material layer, stopping at the patterned hard mask layer; and performing oxygen ion implantation to form an oxygen injection region within the fins and the isolation material layer; back-etching the isolation material layer, stopping above the oxygen injection region, to form a remaining portion of the isolation material layer exposing a portion of the fins; and performing thermal annealing to cause a thermal oxidation of a portion of the fins through oxygen ions in the oxygen injection region, thereby forming an oxide layer within the plurality of fins.

Abstract: A semiconductor device includes a fin structure of a first semiconductor material on a substrate. The fin structure has a source region, a drain region, and a channel region between the source region and the drain region. The device also has a gate structure overlying the fin structure. The source region includes an inner portion of the first semiconductor material and an outer portion of a second semiconductor material overlying a top surface and side surfaces of the inner portion. The drain region includes an inner portion of the first semiconductor material and an outer portion of the second semiconductor material overlying a top surface and side surfaces of the inner portion.

Abstract: The present disclosure provides a semiconductor fabrication method. The method includes providing a semiconductor substrate having first regions and second regions; providing a first gate structure on a first region of the semiconductor substrate, and a second gate structure on a second region of the semiconductor substrate; and forming first trenches in the first region at both sides of the first gate structure. The method further includes forming a first stress layer in the first trenches and a first bumping stress layer on the first stress layer; forming second trenches in a second region at both sides of the second gate structure; and forming a second stress layer in the second trenches and a second bumping stress layer on the second stress layer.

Abstract: A semiconductor device and method of forming the same include a substrate having a plurality of memory cells formed thereon. A memory cell includes pass-gate transistors, pull-up transistors, and pull-down transistors. The pass-gate transistors and a portion of the pull-down transistors have different doping concentrations.

Abstract: A semiconductor device and method of forming the same include a substrate having a plurality of memory cells formed thereon. A memory cell includes pass-gate transistors, pull-up transistors, and pull-down transistors. The pass-gate transistors and a portion of the pull-down transistors have different doping concentrations.

Abstract: A method for fabricating a semiconductor device includes providing a semiconductor substrate, forming on the semiconductor substrate a dummy gate interface layer and a dummy gate of a core device and a gate interface layer and a dummy gate of an IO device, removing the dummy gates of the core and IO devices, removing the dummy gate interface layer of the core device, forming a gate interface layer in the original location of the removed dummy gate interface layer, forming a high-k dielectric layer each on the gate interface layer of the core and IO devices, and submitting the semiconductor substrate to a high-pressure fluorine annealing. The high-pressure fluorine annealing causes the gate interface layer and the high-k dielectric layer of the core and IO devices to be doped with fluoride ions.

Abstract: The present invention provides a multi-working voltages CMOS device with single gate oxide layer thickness, gate work functions of CMOS transistors are regulated by implanting ions with different work functions into metal oxide dielectric material layers of the CMOS transistors, thus to realize different flat-band voltages under the condition of single dielectric layer thickness, and realize a multi-working voltages CMOS structure under the condition of single dielectric layer thickness. The present invention overcomes the process complexity of multiple kinds of gate dielectric layer thicknesses needed by traditional multi-working voltages CMOS, simplifies the CMOS process, makes the manufacturing procedure simple and easy to execute, reduces the preparation cost and is suitable for industrial production.