Patents by Inventor Xiying Costa
Xiying Costa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10573388Abstract: A non-volatile storage system comprises memory cells arranged in groups of memory cells that include programmable select gates and one or more control circuits in communication with the memory cells. The one or more control circuits configured to identify a select gate that needs to be programmed and program the select gate identified to be programmed if a temperature at the non-volatile memory cells is greater than a minimum temperature and defer programming of the select gate identified to be programmed until the temperature at the non-volatile memory cells is greater than the minimum temperature. In some embodiments, the one or more control circuits are configured to perform dummy memory operations on the plurality of non-volatile memory cells to raise the temperature of the non-volatile memory cells in response to determining that the temperature at the non-volatile memory cells is not high enough.Type: GrantFiled: April 4, 2018Date of Patent: February 25, 2020Assignee: Western Digital Technologies, Inc.Inventors: Mahim Raj Gupta, Mohsen Purahmad, Bo Lei, Joanna Lai, Xiying Costa
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Publication number: 20190311770Abstract: A non-volatile storage system comprises memory cells arranged in groups of memory cells that include programmable select gates and one or more control circuits in communication with the memory cells. The one or more control circuits configured to identify a select gate that needs to be programmed and program the select gate identified to be programmed if a temperature at the non-volatile memory cells is greater than a minimum temperature and defer programming of the select gate identified to be programmed until the temperature at the non-volatile memory cells is greater than the minimum temperature. In some embodiments, the one or more control circuits are configured to perform dummy memory operations on the plurality of non-volatile memory cells to raise the temperature of the non-volatile memory cells in response to determining that the temperature at the non-volatile memory cells is not high enough.Type: ApplicationFiled: April 4, 2018Publication date: October 10, 2019Applicant: Western Digital Technologies, Inc.Inventors: Mahim Raj Gupta, Mohsen Purahmad, Bo Lei, Joanna Lai, Xiying Costa
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Patent number: 10388390Abstract: Sensing in non-volatile memory is performed using bias conditions that are dependent on the position of a selected memory cell within a group of non-volatile memory cells. During sensing, a selected memory cell receives a reference voltage while the remaining memory cells receive a read or verify pass voltage. For at least a subset of the unselected memory cells, the pass voltage that is applied is dependent upon the position of the selected memory cell in the group. As programming progresses from a memory cell at a first end of a NAND string toward a memory cell at a second end of the NAND string, for example, the pass voltage for at least a subset of the unselected memory cells that have already been subjected to programming may be increased. This technique may reduce the effects of an increased channel resistance that occurs as more memory cells are programmed.Type: GrantFiled: March 21, 2019Date of Patent: August 20, 2019Assignee: SanDisk Technologies LLCInventor: Xiying Costa
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Publication number: 20190221274Abstract: Sensing in non-volatile memory is performed using bias conditions that are dependent on the position of a selected memory cell within a group of non-volatile memory cells. During sensing, a selected memory cell receives a reference voltage while the remaining memory cells receive a read or verify pass voltage. For at least a subset of the unselected memory cells, the pass voltage that is applied is dependent upon the position of the selected memory cell in the group. As programming progresses from a memory cell at a first end of a NAND string toward a memory cell at a second end of the NAND string, for example, the pass voltage for at least a subset of the unselected memory cells that have already been subjected to programming may be increased. This technique may reduce the effects of an increased channel resistance that occurs as more memory cells are programmed.Type: ApplicationFiled: March 21, 2019Publication date: July 18, 2019Applicant: SanDisk Technologies LLCInventor: Xiying Costa
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Patent number: 10355007Abstract: A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line trench can be filled with a memory film layer, and a plurality of semiconductor channels can straddle the line trench. The back gate electrode can extend along the lengthwise direction of the line trench. In another embodiment, an isolated memory opening overlying a patterned conductive layer can be filled with a memory film, and the back gate electrode can be formed within a semiconductor channel and on the patterned conductive layer. A dielectric cap portion electrically isolates the back gate electrode from a drain region. The back gate electrode can be employed to bias the semiconductor channel, and to enable sensing of multinary bits corresponding to different amounts of electrical charges stored in a memory cell.Type: GrantFiled: December 15, 2016Date of Patent: July 16, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Xiying Costa, Dana Lee, Yanli Zhang, Johann Alsmeier, Yingda Dong, Akira Matsudaira
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Patent number: 10283208Abstract: Sensing in non-volatile memory is performed using bias conditions that are dependent on the position of a selected memory cell within a group of non-volatile memory cells. During sensing, a selected memory cell receives a reference voltage while the remaining memory cells receive a read or verify pass voltage. For at least a subset of the unselected memory cells, the pass voltage that is applied is dependent upon the position of the selected memory cell in the group. As programming progresses from a memory cell at a first end of a NAND string toward a memory cell at a second end of the NAND string, for example, the pass voltage for at least a subset of the unselected memory cells that have already been subjected to programming may be increased. This technique may reduce the effects of an increased channel resistance that occurs as more memory cells are programmed.Type: GrantFiled: July 11, 2018Date of Patent: May 7, 2019Assignee: SanDisk Technologies LLCInventor: Xiying Costa
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Publication number: 20180322935Abstract: Sensing in non-volatile memory is performed using bias conditions that are dependent on the position of a selected memory cell within a group of non-volatile memory cells. During sensing, a selected memory cell receives a reference voltage while the remaining memory cells receive a read or verify pass voltage. For at least a subset of the unselected memory cells, the pass voltage that is applied is dependent upon the position of the selected memory cell in the group. As programming progresses from a memory cell at a first end of a NAND string toward a memory cell at a second end of the NAND string, for example, the pass voltage for at least a subset of the unselected memory cells that have already been subjected to programming may be increased. This technique may reduce the effects of an increased channel resistance that occurs as more memory cells are programmed.Type: ApplicationFiled: July 11, 2018Publication date: November 8, 2018Applicant: SanDisk Technologies LLCInventor: Xiying Costa
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Patent number: 10056399Abstract: A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers, a first memory opening fill structure extending through the first alternating stack and including a first memory film and a first vertical semiconductor channel, a joint-level electrically conductive layer overlying the first alternating stack, at least one joint-level doped semiconductor portion contacting a top surface of the first vertical semiconductor channel and located within, and electrically isolated from, the joint-level electrically conductive layer, a second alternating stack of second insulating layers and second electrically conductive layers located over the joint-level electrically conductive layer, and a second memory opening fill structure extending through the second alternating stack and including a second memory film and a second vertical semiconductor channel that is laterally surrounded by the second memory film and vertically extends into the at leasType: GrantFiled: February 28, 2017Date of Patent: August 21, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Xiying Costa, Daxin Mao, Christopher Petti, Dana Lee, Yao-Sheng Lee
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Patent number: 10049758Abstract: Sensing in non-volatile memory is performed using bias conditions that are dependent on the position of a selected memory cell within a group of non-volatile memory cells. During sensing, a selected memory cell receives a reference voltage while the remaining memory cells receive a read or verify pass voltage. For at least a subset of the unselected memory cells, the pass voltage that is applied is dependent upon the position of the selected memory cell in the group. As programming progresses from a memory cell at a first end of a NAND string toward a memory cell at a second end of the NAND string, for example, the pass voltage for at least a subset of the unselected memory cells that have already been subjected to programming may be increased. This technique may reduce the effects of an increased channel resistance that occurs as more memory cells are programmed.Type: GrantFiled: July 7, 2016Date of Patent: August 14, 2018Assignee: SanDisk Technologies LLCInventor: Xiying Costa
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Publication number: 20180182771Abstract: A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers, a first memory opening fill structure extending through the first alternating stack and including a first memory film and a first vertical semiconductor channel, a joint-level electrically conductive layer overlying the first alternating stack, at least one joint-level doped semiconductor portion contacting a top surface of the first vertical semiconductor channel and located within, and electrically isolated from, the joint-level electrically conductive layer, a second alternating stack of second insulating layers and second electrically conductive layers located over the joint-level electrically conductive layer, and a second memory opening fill structure extending through the second alternating stack and including a second memory film and a second vertical semiconductor channel that is laterally surrounded by the second memory film and vertically extends into the at leasType: ApplicationFiled: February 28, 2017Publication date: June 28, 2018Inventors: Xiying Costa, Daxin Mao, Christopher Petti, Dana Lee, Yao-Sheng Lee
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Publication number: 20180012667Abstract: Sensing in non-volatile memory is performed using bias conditions that are dependent on the position of a selected memory cell within a group of non-volatile memory cells. During sensing, a selected memory cell receives a reference voltage while the remaining memory cells receive a read or verify pass voltage. For at least a subset of the unselected memory cells, the pass voltage that is applied is dependent upon the position of the selected memory cell in the group. As programming progresses from a memory cell at a first end of a NAND string toward a memory cell at a second end of the NAND string, for example, the pass voltage for at least a subset of the unselected memory cells that have already been subjected to programming may be increased. This technique may reduce the effects of an increased channel resistance that occurs as more memory cells are programmed.Type: ApplicationFiled: July 7, 2016Publication date: January 11, 2018Applicant: SanDisk Technologies LLCInventor: Xiying Costa
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Patent number: 9672917Abstract: Systems and methods for implementing and using stacked vertical memory array architectures. A first NAND string may be formed or arranged above a second NAND string. The first NAND string may include a first drain-side select gate connected to a first set of memory cell transistors connected to a first source-side select gate. The second NAND string may include a second drain-side select gate connected to a second set of memory cell transistors connected to a second source-side select gate. The first NAND string and the second NAND string may comprise portions of the same or different memory array architectures (e.g., the first NAND string may be part of a memory array that uses U-shaped NAND strings and the second NAND string may be part of a memory array that uses single vertical NAND strings).Type: GrantFiled: May 26, 2016Date of Patent: June 6, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Xiying Costa, Henry Chien, Yao-Sheng Lee, Yanli Zhang
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Publication number: 20170098655Abstract: A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line trench can be filled with a memory film layer, and a plurality of semiconductor channels can straddle the line trench. The back gate electrode can extend along the lengthwise direction of the line trench. In another embodiment, an isolated memory opening overlying a patterned conductive layer can be filled with a memory film, and the back gate electrode can be formed within a semiconductor channel and on the patterned conductive layer. A dielectric cap portion electrically isolates the back gate electrode from a drain region. The back gate electrode can be employed to bias the semiconductor channel, and to enable sensing of multinary bits corresponding to different amounts of electrical charges stored in a memory cell.Type: ApplicationFiled: December 15, 2016Publication date: April 6, 2017Inventors: Xiying COSTA, Dana LEE, Yanli ZHANG, Johann ALSMEIER, Yingda DONG, Akira MATSUDAIRA
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Patent number: 9515080Abstract: A vertical NAND string device includes a semiconductor channel, where at least one end portion of the semiconductor channel extends substantially perpendicular to a major surface of a substrate, at least one semiconductor or electrically conductive landing pad embedded in the semiconductor channel, a tunnel dielectric located adjacent to the semiconductor channel, a charge storage region located adjacent to the tunnel dielectric, a blocking dielectric located adjacent to the charge storage region and a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate.Type: GrantFiled: March 12, 2014Date of Patent: December 6, 2016Assignee: SANDISK TECHNOLOGIES LLCInventors: Akira Takahashi, Chi-Ming Wang, Johann Alsmeier, Henry Chien, Xiying Costa
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Patent number: 9460799Abstract: Techniques for recovery of partially programmed blocks in non-volatile storage are disclosed. After programming memory cells in an open region of a partially programmed block, a fail bit count with respect to programming the memory cells is performed. If the fail bit count is above a threshold, then a recovery operation is performed of other memory cells in the partially programmed block. The recovery operation (such as erase) may remove charges that are trapped in the tunnel dielectric of memory cells in the open region of the partially programmed block. Note that this erase operation may be performed on memory cells in the open region that are already erased. The erase operation may remove trapped charges from the tunnel dielectric. In a sense, this “resets” the memory cells. Thus, the memory cells can now be programmed more effectively. Both programming and date retention may be improved.Type: GrantFiled: November 24, 2015Date of Patent: October 4, 2016Assignee: SanDisk Technologies LLCInventors: Xiying Costa, Dana Lee, Zhenming Zhou
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Patent number: 9330778Abstract: An erase operation for a 3D stacked memory device assigns storage elements to groups according to an expected erase speed. The storage elements are then erased according to their group to provide a more uniform erase depth and a tighter erase distribution. In one approach, the control gate voltages are set differently for the different groups to slow down the storage elements which are expected to have a faster programming speed. An erase or inhibit status can be set for all groups together. In another approach, the control gate voltages are common for the different groups but an erase or inhibit status is set for each group separately.Type: GrantFiled: October 27, 2014Date of Patent: May 3, 2016Assignee: SanDisk Technologies Inc.Inventors: Xiying Costa, Alex Mak, Johann Alsmeier, Man L Mui
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Patent number: 9331090Abstract: A NAND device has at least a 3×3 array of vertical NAND strings in which the control gate electrodes are continuous in the array and do not have an air gap or a dielectric filled trench in the array. The NAND device is formed by first forming a lower select gate level having separated lower select gates, then forming plural memory device levels containing a plurality of NAND string portions, and then forming an upper select gate level over the memory device levels having separated upper select gates.Type: GrantFiled: October 17, 2014Date of Patent: May 3, 2016Assignee: SANDISK TECHNOLOGIES INC.Inventors: Johann Alsmeier, Raghuveer S. Makala, Xiying Costa, Yanli Zhang
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Patent number: 9240241Abstract: A 3D NAND stacked non-volatile memory device, comprising: a string comprising a plurality of non-volatile storage elements, the string comprises a channel and extends vertically through layers of the 3D stacked non-volatile memory device, and the plurality of storage elements are subdivided into different groups based on group assignments, each group of the different groups comprises multiple adjacent storage elements of the plurality of storage elements; and a control circuit in communication with the string, the control circuit, to perform a Pseudo Block Operation Mode.Type: GrantFiled: December 8, 2014Date of Patent: January 19, 2016Assignee: SanDisk Technologies Inc.Inventors: Xiying Costa, Alexander Kwok-Tung Mak, Chris Avila, Gautam Dusija, Man Mui
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Patent number: 9178149Abstract: This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.Type: GrantFiled: July 7, 2014Date of Patent: November 3, 2015Assignee: Intermolecular, Inc.Inventors: Michael Miller, Tony P. Chiang, Xiying Costa, Tanmay Kumar, Prashant B Phatak, April Schricker
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Patent number: 9177673Abstract: Layers in a multi-layer memory array are categorized according to likely error rates as predicted from their memory hole diameters. Data to be stored along a word line in a high risk layer is subject to a redundancy operation (e.g. XOR) with data to be stored along a word line in a low risk layer so that the risk of both being bad is low.Type: GrantFiled: October 28, 2013Date of Patent: November 3, 2015Assignee: SanDisk Technologies Inc.Inventors: Deepak Raghu, Gautam A. Dusija, Chris Avila, Yingda Dong, Man Mui, Xiying Costa, Pao-Ling Koh