Patents by Inventor Xue-Hung TSAI

Xue-Hung TSAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11120761
    Abstract: A driving substrate includes a substrate, at least one active device, a resistor, a first passivation layer and a second passivation layer. The active device including an oxide semiconductor layer and the resistor coupled to the active device are disposed on the substrate. The first passivation layer covers the active device, wherein a portion of the first passivation layer directly contacts to the oxide semiconductor layer such that the oxide semiconductor layer has a first conductivity. The second passivation layer covers the first passivation layer and the resistor, wherein a portion of the second passivation layer directly contacts to the resistor such that the resistor has a second conductivity. The first conductivity is different from the second conductivity.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: September 14, 2021
    Assignee: E Ink Holdings Inc.
    Inventors: Wei-Tsung Chen, Po-Hsin Lin, Xue-Hung Tsai
  • Publication number: 20210272527
    Abstract: A trace structure of a display panel including a first metal layer and a second metal layer is provided. The first metal layer is configured to transmit a first voltage. The second metal layer is disposed under the first metal layer and configured to transmit a second voltage. The first metal layer and the second metal layer form the trace structure on the display panel, such that the trace structure has a capacitor structure. The trace structure is configured to connect a power input and a panel driver circuit.
    Type: Application
    Filed: March 2, 2021
    Publication date: September 2, 2021
    Applicant: E Ink Holdings Inc.
    Inventors: Xue-Hung Tsai, Wei-Tsung Chen, Po-Hsin Lin
  • Patent number: 10923068
    Abstract: A display device and a display driving circuit with electromagnetic interference suppression capability are provided. The display device includes a substrate, an active matrix, a display driver and a thin-film transistor (TFT) conditioning circuit. The active matrix disposed on the substrate includes multiple data lines, multiple gate lines and multiple pixels. The data lines intersect with the gate lines. The pixels are coupled to intersections of the data lines and the gate lines. The display driver disposed on the substrate generates signals for driving the data lines and/or the gate lines in response to a conditioned serial data clock. The TFT conditioning circuit disposed on the substrate is coupled to the display driver. The TFT conditioning circuit includes one or more TFTs, and attenuates an amplitude of a serial data clock in response to a predetermined gate bias to provide the conditioned serial data clock to the display driver.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: February 16, 2021
    Assignee: E INK HOLDINGS INC.
    Inventors: Xue-Hung Tsai, Wei-Tsung Chen, Yu-Lin Wang, Po-Hsin Lin
  • Patent number: 10672623
    Abstract: A method of manufacturing a transistor, includes: (i) forming a metal-oxide semiconductor layer over a substrate; (ii) forming a source electrode and a drain electrode on different sides of the metal-oxide semiconductor layer; (iii) forming a dielectric layer over the source electrode, the drain electrode, and the metal-oxide semiconductor layer; (iv) forming a hydrogen-containing insulating layer over the dielectric layer, in which the hydrogen-containing insulating layer has an aperture exposing a surface of the dielectric layer, and the aperture is overlapped with the metal-oxide semiconductor layer when viewed in a direction perpendicular to the surface; (v) increasing a hydrogen concentration of a portion of the metal-oxide semiconductor layer by treating the hydrogen-containing insulating layer so to form a source region and a drain region; and (vi) forming a gate electrode in the aperture.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: June 2, 2020
    Assignee: E Ink Holdings Inc.
    Inventors: Wei-Tsung Chen, Po-Hsin Lin, Xue-Hung Tsai
  • Publication number: 20190362685
    Abstract: A display device and a display driving circuit with electromagnetic interference suppression capability are provided. The display device includes a substrate, an active matrix, a display driver and a thin-film transistor (TFT) conditioning circuit. The active matrix disposed on the substrate includes multiple data lines, multiple gate lines and multiple pixels. The data lines intersect with the gate lines. The pixels are coupled to intersections of the data lines and the gate lines. The display driver disposed on the substrate generates signals for driving the data lines and/or the gate lines in response to a conditioned serial data clock. The TFT conditioning circuit disposed on the substrate is coupled to the display driver. The TFT conditioning circuit includes one or more TFTs, and attenuates an amplitude of a serial data clock in response to a predetermined gate bias to provide the conditioned serial data clock to the display driver.
    Type: Application
    Filed: May 22, 2019
    Publication date: November 28, 2019
    Applicant: E Ink Holdings Inc.
    Inventors: Xue-Hung TSAI, Wei-Tsung CHEN, Yu-Lin WANG, Po-Hsin LIN
  • Publication number: 20190122628
    Abstract: A driving substrate includes a substrate, at least one active device, a resistor, a first passivation layer and a second passivation layer. The active device including an oxide semiconductor layer and the resistor coupled to the active device are disposed on the substrate. The first passivation layer covers the active device, wherein a portion of the first passivation layer directly contacts to the oxide semiconductor layer such that the oxide semiconductor layer has a first conductivity. The second passivation layer covers the first passivation layer and the resistor, wherein a portion of the second passivation layer directly contacts to the resistor such that the resistor has a second conductivity. The first conductivity is different from the second conductivity.
    Type: Application
    Filed: October 16, 2018
    Publication date: April 25, 2019
    Applicant: E Ink Holdings Inc.
    Inventors: Wei-Tsung Chen, Po-Hsin Lin, Xue-Hung Tsai
  • Publication number: 20190115227
    Abstract: A method of manufacturing a transistor, includes: (i) forming a metal-oxide semiconductor layer over a substrate; (ii) forming a source electrode and a drain electrode on different sides of the metal-oxide semiconductor layer; (iii) forming a dielectric layer over the source electrode, the drain electrode, and the metal-oxide semiconductor layer; (iv) forming a hydrogen-containing insulating layer over the dielectric layer, in which the hydrogen-containing insulating layer has an aperture exposing a surface of the dielectric layer, and the aperture is overlapped with the metal-oxide semiconductor layer when viewed in a direction perpendicular to the surface; (v) increasing a hydrogen concentration of a portion of the metal-oxide semiconductor layer by treating the hydrogen-containing insulating layer so to form a source region and a drain region; and (vi) forming a gate electrode in the aperture.
    Type: Application
    Filed: December 6, 2018
    Publication date: April 18, 2019
    Inventors: Wei-Tsung CHEN, Po-Hsin LIN, Xue-Hung TSAI
  • Patent number: 10193022
    Abstract: A pixel structure includes a substrate, a gate electrode disposed on the substrate, a capacitor electrode disposed on the substrate, a first insulation layer, an active layer disposed on the first insulation layer, a drain electrode, a source electrode and an extension electrode. The capacitor electrode is spaced apart from the gate electrode. The first insulation layer covers the gate electrode and the capacitor electrode. The first insulation layer has a recess vertically above the capacitor electrode. The drain and the source electrodes are disposed on the active layer and spaced apart from each other. The extension electrode extends from the drain electrode or the source electrode into the recess.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: January 29, 2019
    Assignee: E Ink Holdings Inc.
    Inventors: Xue-Hung Tsai, Wei-Tsung Chen, Henry Wang, Po-Hsin Lin
  • Patent number: 10186430
    Abstract: A method of manufacturing a transistor, includes: (i) forming a metal-oxide semiconductor layer over a substrate; (ii) forming a source electrode and a drain electrode on different sides of the metal-oxide semiconductor layer; (iii) forming a dielectric layer over the source electrode, the drain electrode, and the metal-oxide semiconductor layer; (iv) forming a hydrogen-containing insulating layer over the dielectric layer, in which the hydrogen-containing insulating layer has an aperture exposing a surface of the dielectric layer, and the aperture is overlapped with the metal-oxide semiconductor layer when viewed in a direction perpendicular to the surface; (v) increasing a hydrogen concentration of a portion of the metal-oxide semiconductor layer by treating the hydrogen-containing insulating layer so to form a source region and a drain region; and (vi) forming a gate electrode in the aperture.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: January 22, 2019
    Assignee: E Ink Holdings Inc.
    Inventors: Wei-Tsung Chen, Po-Hsin Lin, Xue-Hung Tsai
  • Publication number: 20180323342
    Abstract: A pixel structure includes a substrate, a gate electrode disposed on the substrate, a capacitor electrode disposed on the substrate, a first insulation layer, an active layer disposed on the first insulation layer, a drain electrode, a source electrode and an extension electrode. The capacitor electrode is spaced apart from the gate electrode. The first insulation layer covers the gate electrode and the capacitor electrode. The first insulation layer has a recess vertically above the capacitor electrode. The drain and the source electrodes are disposed on the active layer and spaced apart from each other. The extension electrode extends from the drain electrode or the source electrode into the recess.
    Type: Application
    Filed: November 17, 2017
    Publication date: November 8, 2018
    Inventors: Xue-Hung TSAI, Wei-Tsung CHEN, Henry WANG, Po-Hsin LIN
  • Patent number: 10054810
    Abstract: A display apparatus includes at least one pixel structure, which includes an active device, an electric insulation layer and a pixel electrode. The electric insulation layer is disposed on the active device. The electric insulation layer has a trench and a via. The via is located on a bottom surface of the trench. A portion of the electric insulation layer surrounding the trench is monolithically connected to another portion of the electric insulation layer surrounding the via. A pixel electrode has a first electrode portion and a second electrode portion connected to each other. The first electrode portion is located in the trench. A thickness of the first electrode portion is less than a depth of the trench. The second electrode portion is located in the via and is electrically connected to the active device through the via.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: August 21, 2018
    Assignee: E Ink Holdings Inc.
    Inventors: Xue-Hung Tsai, Wei-Tsung Chen, Henry Wang, Po-Hsin Lin
  • Publication number: 20180088397
    Abstract: A display apparatus includes at least one pixel structure, which includes an active device, an electric insulation layer and a pixel electrode. The electric insulation layer is disposed on the active device. The electric insulation layer has a trench and a via. The via is located on a bottom surface of the trench. A portion of the electric insulation layer surrounding the trench is monolithically connected to another portion of the electric insulation layer surrounding the via. A pixel electrode has a first electrode portion and a second electrode portion connected to each other. The first electrode portion is located in the trench. A thickness of the first electrode portion is less than a depth of the trench. The second electrode portion is located in the via and is electrically connected to the active device through the via.
    Type: Application
    Filed: July 6, 2017
    Publication date: March 29, 2018
    Inventors: Xue-Hung TSAI, Wei-Tsung CHEN, Henry WANG, Po-Hsin LIN
  • Publication number: 20180047587
    Abstract: A method of manufacturing a transistor, includes: (i) forming a metal-oxide semiconductor layer over a substrate; (ii) forming a source electrode and a drain electrode on different sides of the metal-oxide semiconductor layer; (iii) forming a dielectric layer over the source electrode, the drain electrode, and the metal-oxide semiconductor layer; (iv) forming a hydrogen-containing insulating layer over the dielectric layer, in which the hydrogen-containing insulating layer has an aperture exposing a surface of the dielectric layer, and the aperture is overlapped with the metal-oxide semiconductor layer when viewed in a direction perpendicular to the surface; (v) increasing a hydrogen concentration of a portion of the metal-oxide semiconductor layer by treating the hydrogen-containing insulating layer so to form a source region and a drain region; and (vi) forming a gate electrode in the aperture.
    Type: Application
    Filed: May 12, 2017
    Publication date: February 15, 2018
    Inventors: Wei-Tsung CHEN, Po-Hsin LIN, Xue-Hung TSAI
  • Patent number: 9825140
    Abstract: A metal oxide thin film transistor (TFT) includes a gate electrode, a gate insulating layer, a metal oxide active layer, a source electrode, and a drain electrode. The gate electrode is formed on a substrate. The gate insulating layer is formed on the substrate and covers the gate electrode. The metal oxide active layer is formed on the gate insulating layer. The drain electrode and the source electrode are formed on two opposite ends of the metal oxide active layer in a spaced-apart manner, in which at least one of the orthographic projection of the source electrode and the orthographic projection of the drain electrode on the substrate does not overlap the gate electrode.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: November 21, 2017
    Assignee: E Ink Holdings Inc.
    Inventors: Chia-Chun Yeh, Henry Wang, Xue-Hung Tsai, Chih-Hsuan Wang
  • Patent number: 9520451
    Abstract: An organic light-emitting diode display device includes a substrate, a light-absorption layer, an active array structure, and an organic light-emitting diode. The substrate has a first and a second surface opposite to each other. The light-absorption layer is disposed on the first surface, and has at least one opening exposing a portion of the first surface. The active array structure is positioned on the second surface, and includes at least one data line, at least one gate line, and at least one switching device electrically connected to the gate and data lines. The light-absorption layer overlaps at least one of the data line and the gate line when viewed in a direction perpendicular to the substrate. The organic light-emitting diode is electrically connected to the switching device, and the organic light-emitting diode overlaps the opening when viewed in the direction perpendicular to the substrate.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: December 13, 2016
    Assignee: E Ink Holdings Inc.
    Inventors: Wei-Chou Lan, Ted-Hong Shinn, Xue-Hung Tsai, Chi-Liang Wu, Chih-Hsiang Yang
  • Patent number: 9431542
    Abstract: A semiconductor structure includes a top gate, an oxide semiconductor channel layer, a first dielectric layer, a second dielectric layer, a source and a drain. The oxide semiconductor channel layer is disposed between the top gate and a substrate. The first dielectric layer is disposed between the top gate and the oxide semiconductor channel layer. The second dielectric layer is disposed between the first dielectric layer and the oxide semiconductor channel layer. The source and the drain are disposed on two opposite sides of the oxide semiconductor channel layer and located between the first dielectric layer and the substrate. A portion of the oxide semiconductor channel layer is exposed between the source and the drain. A portion of the first dielectric layer and a portion of the second dielectric layer directly contact with and entirely cover the portion of the oxide semiconductor channel layer.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: August 30, 2016
    Assignee: E Ink Holdings Inc.
    Inventors: Wei-Tsung Chen, Chuang-Chuang Tsai, Ted-Hong Shinn, Xue-Hung Tsai, Chih-Hsiang Yang
  • Patent number: 9368634
    Abstract: A thin film transistor (TFT) including a gate, a dielectric layer, a metal-oxide semiconductor channel, a source, and a drain is provided. The gate and the metal-oxide semiconductor channel are overlapped. The gate, the source, and the drain are separated by the dielectric layer. Besides, the source and the drain are respectively located on two opposite sides of the metal-oxide semiconductor channel. The metal-oxide semiconductor channel includes a metal-oxide semiconductor layer and a plurality of nano micro structures disposed in the metal-oxide semiconductor layer and separated from one another. In another aspect, a display panel including the TFT and a method of fabricating the TFT are also provided.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 14, 2016
    Assignee: E Ink Holdings Inc.
    Inventors: Hsiao-Wen Zan, Chuang-Chuang Tsai, Xue-Hung Tsai, Henry Wang, Wei-Tsung Chen
  • Publication number: 20150357475
    Abstract: A metal oxide thin film transistor (TFT) includes a gate electrode, a gate insulating layer, a metal oxide active layer, a source electrode, and a drain electrode. The gate electrode is formed on a substrate. The gate insulating layer is formed on the substrate and covers the gate electrode. The metal oxide active layer is formed on the gate insulating layer. The drain electrode and the source electrode are formed on two opposite ends of the metal oxide active layer in a spaced-apart manner, in which at least one of the orthographic projection of the source electrode and the orthographic projection of the drain electrode on the substrate does not overlap the gate electrode.
    Type: Application
    Filed: August 13, 2015
    Publication date: December 10, 2015
    Inventors: Chia-Chun YEH, Henry WANG, Xue-Hung TSAI, Chih-Hsuan WANG
  • Patent number: 9142628
    Abstract: A metal oxide thin film transistor (TFT) includes a gate electrode, a gate insulating layer, a metal oxide active layer, a source electrode, and a drain electrode. The gate electrode is formed on a substrate. The gate insulating layer is formed on the substrate and covers the gate electrode. The metal oxide active layer is formed on the gate insulating layer. The drain electrode and the source electrode are formed on two opposite ends of the metal oxide active layer in a spaced-apart manner, in which at least one of the orthographic projection of the source electrode and the orthographic projection of the drain electrode on the substrate does not overlap the gate electrode.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: September 22, 2015
    Assignee: E Ink Holdings Inc.
    Inventors: Chia-Chun Yeh, Henry Wang, Xue-Hung Tsai, Chih-Hsuan Wang
  • Patent number: 9123691
    Abstract: Disclosed herein is a thin film transistor. The thin film transistor is characterized in having a source interconnect layer and a drain interconnect layer. The source electrode and the drain electrode are respectively disposed above and in contact with the source interconnect layer and the drain interconnect layer. The semiconductor layer is in contact with both the source interconnect layer and the drain interconnect layer, but is not in contact with the source electrode and the drain electrode.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 1, 2015
    Assignee: E Ink Holdings Inc.
    Inventors: Henry Wang, Chia-Chun Yeh, Xue-Hung Tsai, Chih-Hsuan Wang, Ted-Hong Shinn