Patents by Inventor Xuebin Yao
Xuebin Yao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12293097Abstract: Provided are systems, methods, and apparatuses for computational offload to storage systems. The method can include a first processing element issuing a first request to the storage device; a storage device, responsive to the first request, obtaining first data on the storage device and providing the first data to the first memory for storage; the second processing element reading the first data from the first memory and performing at least one of an operation or a computation on the first data to generate second data; and the second processing element providing the second data to the first processing element.Type: GrantFiled: January 4, 2022Date of Patent: May 6, 2025Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Mohammadreza Soltaniyeh, Veronica Lagrange Moutinho Dos Reis, Matthew Bryson, Xuebin Yao
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Patent number: 12271322Abstract: A multi-function device is disclosed. A first port may be used to communicate with a host processor. A second port may be used to communicate with a storage device. A third port may be used to communicate with a computational storage unit. Circuit may be used to route a message from the host processor to at least one of the storage device or the computational storage unit.Type: GrantFiled: February 10, 2022Date of Patent: April 8, 2025Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ramdas P. Kachare, Hingkwan Huen, Jimmy Lau, Howard R. Butler, Xuebin Yao
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Patent number: 12271767Abstract: A device is disclosed. A receiver may receive a portion using a first data format from a source device. A transformation unit may transform the portion into a transformed portion. The transformed portion may use a second data format. A transmitter may deliver the transformed portion to a destination device.Type: GrantFiled: February 3, 2023Date of Patent: April 8, 2025Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Mohammadreza Soltaniyeh, Xuebin Yao, Ramdas Kachare
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Publication number: 20250077446Abstract: According to one general aspect, a device may include a host interface circuit configured to communicate with a host device via a data protocol that employs data messages. The device may include a storage element configured to store data in response to a data message. The host interface circuit may be configured to detect when a tunneling command is embedded within the data message; extract a tunneled message address information from the data message; retrieve, via the tunneled message address information, a tunneled message stored in a memory of the host device; and route the tunneled message to an on-board processor and/or data processing logic. The on-board processor and/or data processing logic may be configured to execute one or more instructions in response to the tunneled message.Type: ApplicationFiled: November 18, 2024Publication date: March 6, 2025Inventors: Ramdas P. KACHARE, Zvi GUZ, Son T. PHAM, Anahita SHAYESTEH, Xuebin YAO, Oscar Prem PINTO
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Publication number: 20250071301Abstract: A system and method for in-storage video processing. In some embodiments, the system includes a computational storage device, the computational storage device including non-volatile storage and a processing circuit. The processing circuit may be configured to process a first data unit and to process a second data unit, in parallel with the first data unit.Type: ApplicationFiled: November 8, 2023Publication date: February 27, 2025Inventors: Gongjin SUN, Ramdas KACHARE, Mohammadreza SOLTANIYEH, Caroline KAHN, Xuebin YAO
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Patent number: 12197773Abstract: An device is disclosed. A first buffer to store a query data point, and a second buffer to store a matrix of candidate data points. A processing element may process the query data point and the matrix of candidate data points to identify candidate data points in the matrix of candidate data points that are nearest to the query data point.Type: GrantFiled: January 7, 2022Date of Patent: January 14, 2025Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Erfan Bank Tavakoli, Xuebin Yao, Amir Beygi
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Publication number: 20240419450Abstract: Systems and methods for parallel data processing. In some embodiments, the system includes: a first processing chain; and a second processing chain, the first processing chain including: a first core; a second core; and a first inter-core bus connecting the second core of the first processing chain to the first core of the first processing chain the system being configured to forward an output of a calculation of the first processing chain to the second processing chain.Type: ApplicationFiled: November 10, 2023Publication date: December 19, 2024Inventors: Mohammadreza SOLTANIYEH, Xuebin YAO, Ramdas KACHARE
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Patent number: 12147358Abstract: According to one general aspect, a device may include a host interface circuit configured to communicate with a host device via a data protocol that employs data messages. The device may include a storage element configured to store data in response to a data message. The host interface circuit may be configured to detect when a tunneling command is embedded within the data message; extract a tunneled message address information from the data message; retrieve, via the tunneled message address information, a tunneled message stored in a memory of the host device; and route the tunneled message to an on-board processor and/or data processing logic. The on-board processor and/or data processing logic may be configured to execute one or more instructions in response to the tunneled message.Type: GrantFiled: August 14, 2023Date of Patent: November 19, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ramdas P. Kachare, Zvi Guz, Son T. Pham, Anahita Shayesteh, Xuebin Yao, Oscar Prem Pinto
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Publication number: 20240320182Abstract: A data storage device includes: a data storage medium; a processor comprising a plurality of processor cores; a plurality of application acceleration black-box (AABB) slots including reconfigurable logic blocks, interconnects, and memories; a host interface that receives a host command from a remote application running on a remote host computer, wherein the host command includes an image file including a register-transfer level (RTL) bitstream and a firmware driver; and a configuration controller that downloads the RTL bitstream to an AABB slot of the plurality of AABB slots and reconfigure the AABB slot, and load the firmware driver to a processor core of the processor. The processor core loaded with the firmware driver runs a data acceleration process of the remote application to access and process data stored in the data storage medium using the RTL bitstream downloaded in the AABB slot.Type: ApplicationFiled: May 29, 2024Publication date: September 26, 2024Inventors: Ramdas Kachare, Fred Worley, Xuebin Yao
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Patent number: 12038818Abstract: A storage device configured for hardware verification is disclosed. The storage device comprises a first hardware component comprising a connector and a first verification logic. The first validation logic is configured to detect a criterion and generate a first signal via the connector in response to detecting the criterion. The storage device also comprises a second hardware component coupled to the first hardware component via the connector. The second hardware component comprises a second validation logic, where the second validation logic is configured to monitor and receive the first signal via the connector. In response to receiving the first signal, the second validation logic is configured to compare the received first signal to an expected signal and generate a result. The storage device is configured to take an action in response to the result.Type: GrantFiled: January 30, 2023Date of Patent: July 16, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Sompong Paul Olarig, Xuebin Yao
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Publication number: 20240211418Abstract: A multi-function device is disclosed. A first port may be used to communicate with a host processor. A second port may be used to communicate with a storage device. A third port may be used to communicate with a computational storage unit. Circuit may be used to route a message from the host processor to at least one of the storage device or the computational storage unit.Type: ApplicationFiled: February 10, 2022Publication date: June 27, 2024Inventors: Ramdas P. KACHARE, Hingkwan HUEN, Jimmy LAU, Howard R. BUTLER, Xuebin YAO
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Publication number: 20240184641Abstract: A device is disclosed. A receiver may receive a portion using a first data format from a source device. A transformation unit may transform the portion into a transformed portion. The transformed portion may use a second data format. A transmitter may deliver the transformed portion to a destination device.Type: ApplicationFiled: February 3, 2023Publication date: June 6, 2024Inventors: Mohammadreza SOLTANIYEH, Xuebin YAO, Ramdas KACHARE
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Patent number: 12001374Abstract: A data storage device includes: a data storage medium; a processor comprising a plurality of processor cores; a plurality of application acceleration black-box (AABB) slots including reconfigurable logic blocks, interconnects, and memories; a host interface that receives a host command from a remote application running on a remote host computer, wherein the host command includes an image file including a register-transfer level (RTL) bitstream and a firmware driver; and a configuration controller that downloads the RTL bitstream to an AABB slot of the plurality of AABB slots and reconfigure the AABB slot, and load the firmware driver to a processor core of the processor. The processor core loaded with the firmware driver runs a data acceleration process of the remote application to access and process data stored in the data storage medium using the RTL bitstream downloaded in the AABB slot.Type: GrantFiled: September 26, 2022Date of Patent: June 4, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Ramdas Kachare, Fred Worley, Xuebin Yao
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Publication number: 20240070199Abstract: Methods and memory devices are provided in which at least one parser of a memory device converts graph input data into an edge list and a vertex list for a graph database. A merge sorter of the memory device sorts the vertex list to generate a sequential list of vertices. The edge list is converted into a translated list of edges using identifiers (IDs) of the sequential list of vertices. The merge sorter sorts the translated list of edges to generate a sequential list of edges. The graph database is generated using the sequential list of edges.Type: ApplicationFiled: August 28, 2023Publication date: February 29, 2024Inventors: Seongyoung KANG, Mohammadreza SOLTANIYEH, Xuebin YAO
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Patent number: 11902422Abstract: A device includes a communications circuit configured to communicate with a storage device controller and a host device. The device further includes a processing device configured to receive a request from the storage device controller through the communications circuit. The request requests encrypted data be written to a memory address of the host device. The processing device is further configured to identify a key associated with the write request based on the memory address. The processing device is further configured to generate a decrypted version of the data based on the key. The processing device is further configured to initiate transfer, through the communications circuit, of the decrypted version of the data to the host device.Type: GrantFiled: December 28, 2022Date of Patent: February 13, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Ramdas P. Kachare, Xuebin Yao, Jimmy K. Lau
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Publication number: 20230393996Abstract: According to one general aspect, a device may include a host interface circuit configured to communicate with a host device via a data protocol that employs data messages. The device may include a storage element configured to store data in response to a data message. The host interface circuit may be configured to detect when a tunneling command is embedded within the data message; extract a tunneled message address information from the data message; retrieve, via the tunneled message address information, a tunneled message stored in a memory of the host device; and route the tunneled message to an on-board processor and/or data processing logic. The on-board processor and/or data processing logic may be configured to execute one or more instructions in response to the tunneled message.Type: ApplicationFiled: August 14, 2023Publication date: December 7, 2023Inventors: Ramdas P. KACHARE, Zvi GUZ, Son T. PHAM, Anahita SHAYESTEH, Xuebin YAO, Oscar Prem PINTO
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Patent number: 11726930Abstract: According to one general aspect, a device may include a host interface circuit configured to communicate with a host device via a data protocol that employs data messages. The device may include a storage element configured to store data in response to a data message. The host interface circuit may be configured to detect when a tunneling command is embedded within the data message; extract a tunneled message address information from the data message; retrieve, via the tunneled message address information, a tunneled message stored in a memory of the host device; and route the tunneled message to an on-board processor and/or data processing logic. The on-board processor and/or data processing logic may be configured to execute one or more instructions in response to the tunneled message.Type: GrantFiled: June 3, 2021Date of Patent: August 15, 2023Inventors: Ramdas P. Kachare, Zvi Guz, Son T. Pham, Anahita Shayesteh, Xuebin Yao, Oscar Prem Pinto
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Publication number: 20230168984Abstract: A storage device configured for hardware verification is disclosed. The storage device comprises a first hardware component comprising a connector and a first verification logic. The first validation logic is configured to detect a criterion and generate a first signal via the connector in response to detecting the criterion. The storage device also comprises a second hardware component coupled to the first hardware component via the connector. The second hardware component comprises a second validation logic, where the second validation logic is configured to monitor and receive the first signal via the connector. In response to receiving the first signal, the second validation logic is configured to compare the received first signal to an expected signal and generate a result. The storage device is configured to take an action in response to the result.Type: ApplicationFiled: January 30, 2023Publication date: June 1, 2023Inventors: Sompong Paul Olarig, Xuebin Yao
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Publication number: 20230168556Abstract: The present application provides an array substrate and a display panel. The array substrate includes a substrate and a thin film transistor layer. The thin film transistor layer includes a first metal layer and a second metal layer, the first metal layer includes at least one first metal trace, the second metal layer includes at least one second metal trace, the thin film transistor layer includes a trace crossover area, a barrier layer is disposed between the first metal layer and the second metal layer, and the barrier layer at least covers the trace crossover area.Type: ApplicationFiled: July 9, 2020Publication date: June 1, 2023Applicant: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.Inventors: Xuebin YAO, Bangyin PENG, Ilgon KIM
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Publication number: 20230137282Abstract: A device includes a communications circuit configured to communicate with a storage device controller and a host device. The device further includes a processing device configured to receive a request from the storage device controller through the communications circuit. The request requests encrypted data be written to a memory address of the host device. The processing device is further configured to identify a key associated with the write request based on the memory address. The processing device is further configured to generate a decrypted version of the data based on the key. The processing device is further configured to initiate transfer, through the communications circuit, of the decrypted version of the data to the host device.Type: ApplicationFiled: December 28, 2022Publication date: May 4, 2023Inventors: Ramdas P. Kachare, Xuebin Yao, Jimmy K. Lau