Abstract: A thin film transistor, a manufacturing method thereof, an array substrate and a display panel are provided. The thin film transistor includes: a base substrate; and a gate electrode, a gate insulating layer, an active layer and a source/drain electrode layer which are on the base substrate. The source/drain electrode layer includes a source electrode and a drain electrode. The thin film transistor further includes a light blocking layer surrounding the active layer.

Abstract: The embodiments of the disclosure relate to the field of display technology and provide a counter substrate, a liquid crystal display panel and a method for eliminating bright spots, which can avoid bright spots caused by foreign bodies and reduce cost. The counter substrate includes a substrate, a black matrix and an orientation layer disposed on the substrate, and a wall. The black matrix at least includes a plurality of first light shielding strips. An orthographic projection of the wall on the substrate is covered by an orthographic projection of the plurality of first light shielding strips on the substrate. The wall extends along a first direction that intersects an orientation direction of the orientation layer.

Abstract: A display substrate having pre-tilt angle for liquid crystal molecules and a manufacturing method thereof and a display device are provided. The display substrate includes a plurality of pixel regions, an alignment film for providing a pre-tilt angle for liquid crystal molecules being disposed in the plurality of pixel regions. In each of the pixel regions, a surface of the alignment film has a plurality of orientation grooves extending along at least two directions.

Abstract: The present disclosure provides an array substrate, a display panel, manufacturing methods thereof and a display device. The array substrate includes a display region and a non-display region. The non-display region includes a sealant region arranged at a periphery of the display region and a peripheral region arranged at a periphery of the sealant region. The array substrate further includes a plurality of signal connection lines for connecting driving lines. The signal connection lines include a first connection line, a portion of which is arranged at the peripheral region and another portion of which is arranged at the sealant region.

Abstract: The present disclosure provides an array substrate. The array substrate includes a display region and a plurality of control lines, the display region being divided into a plurality of sub-regions, each sub-region comprising a plurality of pixels, each pixel including a common electrode. Common electrodes in pixels in a sub-region are electrically connected together; common electrodes in two sub-regions are connected by a switching unit; and a control line is connected with the common electrodes in the sub-region to provide a common voltage signal to the common electrodes.

Abstract: A display panel, a method for testing a cell gap thereof, and a display device are disclosed. The display panel includes a first substrate and a second substrate arranged opposite to each other, wherein a light shielding layer is provided on a side of the first substrate close to the second substrate, a portion of the light shielding layer located in a peripheral region includes a plurality of opening areas arranged at intervals, each opening area being provided with a light transmissive layer; and wherein the second substrate has a light transmissive area, an orthographic projection of the light transmissive layer on the second substrate at least partly overlaps with the light transmissive area on the second substrate.

Abstract: An array substrate and a method for manufacturing the same, and a display device are provided. The method includes: forming a thin film transistor (TFT) structure of a display region and a TFT structure of the GOA region on a substrate; sequentially forming a first insulating layer, an indium tin oxide (ITO) layer and a photoresist layer on the TFT structure; exposing and developing the photoresist layer using a halftone mask plate, and etching the ITO layer, to form an electrode layer in the GOA region and an electrode layer in the display region; and ashing the remaining photoresist to completely remove the photoresist on the electrode layer in the display region and to thinning the photoresist on the electrode layer in the GOA region.

Abstract: The present disclosure provides a display substrate, a fabricating method thereof, and a display apparatus including the display substrate. The display substrate includes a plurality of data lines and a plurality of common electrode lines. Each data line extends substantially along a first direction, and each common electrode line is along the first direction, and is configured such that a common electrode signal along the each common electrode line is substantially uniform. Each common electrode line can be substantially parallel to one data line to thereby substantially avoid a pulling effect on the common electrode signal along the each common electrode line caused by coupling between the each common electrode line and the one data line.

Abstract: An array substrate, a display device and a driving method thereof. Gate-line extension lines, data-line extension lines and a control circuit are disposed in a peripheral area of the array substrate. The control circuit is configured to connect the gate lines to the gate-line extension lines and connect the data lines to the data-line extension lines in a time period of displaying an image, and configured to disconnect the gate lines from the gate-line extension lines, disconnect the data lines from the data-line extension lines, control at least part of the gate-line extension lines to have potential difference, and control at least part of the data-line extension lines to have potential difference in a time period between displaying two adjacent images.

Abstract: The present application discloses a display panel including an array substrate and an opposing substrate facing the array substrate; a data line layer having a plurality of data lines on the array substrate; a passivation layer on a side of the data line layer proximal to the opposing substrate; a sealant layer on a side of the passivation layer distal to the data line layer, sealing the array substrate and the opposing substrate together; the display panel having a first area enclosed by the sealant layer and a second area outside of the first area and the sealant layer; the plurality of data lines extending from the first area into the second area; and a common electrode layer on a side of the sealant layer distal to the passivation layer.

Abstract: The disclosure relates to an array substrate, a display panel, a display device, and methods of manufacturing them. The array substrate includes: a base substrate, a first electrode, a first insulating layer, and a second electrode, the second electrode having a plurality of second electrode portions spaced apart from one another, the first electrode having overlapped portions that overlap the plurality of second electrode portions, the first electrode is one of a common electrode and a pixel electrode and the second electrode is the other; at least one of the second electrode and the overlapped portions has a recess recessing towards the base substrate and an area of an opening of the recess is larger than an area of a bottom of the recess.

Abstract: An array substrate, a display device and a driving method thereof. Gate-line extension lines, data-line extension lines and a control circuit are disposed in a peripheral area of the array substrate. The control circuit is configured to connect the gate lines to the gate-line extension lines and connect the data lines to the data-line extension lines in a time period of displaying an image, and configured to disconnect the gate lines from the gate-line extension lines, disconnect the data lines from the data-line extension lines, control at least part of the gate-line extension lines to have potential difference, and control at least part of the data-line extension lines to have potential difference in a time period between displaying two adjacent images.

Abstract: An array substrate, a manufacturing method thereof and a display panel are disclosed. The array substrate comprises: a base substrate (200) and gate lines (202), data lines (205) and a plurality of pixel units (20). Each pixel unit (20) includes a first thin-film transistor (TFT), a pixel electrode (208) and at least second TFT connected in series with the first TFT. The pixel electrode (208) is connected with a drain electrode (207) of the second TFT; a source electrode (206?) of the second TFT is connected with a drain electrode (207) of the first TFT; and a source electrode (206) of the first TFT is connected with the data line (205). The array substrate can reduce the leakage current when the TFTs are switched off.

Abstract: An array substrate and a method for manufacturing the same, and a display device are provided. The method includes: forming a thin film transistor (TFT) structure of a display region and a TFT structure of the GOA region on a substrate; sequentially forming a first insulating layer, an indium tin oxide (ITO) layer and a photoresist layer on the TFT structure; exposing and developing the photoresist layer using a halftone mask plate, and etching the ITO layer, to form an electrode layer in the GOA region and an electrode layer in the display region; and ashing the remaining photoresist to completely remove the photoresist on the electrode layer in the display region and to thinning the photoresist on the electrode layer in the GOA region.

Abstract: A display substrate and a manufacturing method thereof and a display device are disclosed. The display substrate includes a plurality of pixel regions, an alignment film for providing a pre-tilt angle for liquid crystal molecules being disposed in the plurality of pixel regions. In each of the pixel regions, a surface of the alignment film has a plurality of orientation grooves extending along at least two directions. The alignment film is made of a transparent material, and therefore, an aperture ratio of pixels will not be affected, and an influence on other structures of the display substrate either will not be generated.

Abstract: A measuring device and method for a substrate warping amount includes a first substrate and a second substrate disposed oppositely. The measuring device includes a light source, a measuring eyepiece and a processor. The light source is configured to emit a monochromatic light to a region to be measured of the display motherboard, and form a Newton ring interference pattern. The measuring eyepiece is configured to acquire the Newton ring interference pattern and measure a diameter and a corresponding order number of each interference fringe in the Newton ring interference pattern. The processor is connected to the measuring eyepiece and configured to obtain a thickness of an air layer at each interference fringe according to the diameter and the corresponding order number of each interference fringe and a wavelength of the monochromatic light, to obtain a warping amount of the region to be measured of the display motherboard.

Abstract: The present disclosure provides a display substrate assembly including a first substrate and a second substrate opposite to each other, the first substrate including a first region and a second region, and, a total thickness of functional layers within the first region being less than a total thickness of functional layers within the second region, of the first substrate. A thickness compensation layer is provided on at least one of the first substrate and the second substrate, a position of the thickness compensation layer corresponds to a position of the first region, and, a sum of thickness of a thickness of the thickness compensation layer and the total thickness of the functional layers within the first region equals to the total thickness of the functional layers within the second region.

Abstract: The present disclosure provides an array substrate. The array substrate includes a display region and a plurality of control lines, the display region being divided into a plurality of sub-regions, each sub-region comprising a plurality of pixels, each pixel including a common electrode. Common electrodes in pixels in a sub-region are electrically connected together; common electrodes in two sub-regions are connected by a switching unit; and a control line is connected with the common electrodes in the sub-region to provide a common voltage signal to the common electrodes.

Abstract: Embodiments of the present disclosure relates to a liquid crystal drop filling system comprising a liquid crystal drop filling device performing a liquid crystal drop filling process to obtain a liquid crystal panel; an image acquisition device acquiring an image of the liquid crystal panel; an image processor processing the acquired image and determining a defect of the liquid crystal panel based on the processed image; and a communication module communicating an information about the defect determined by the image processor to the liquid crystal drop filling device, so that the liquid crystal drop filling device can adjust parameters of the liquid crystal drop filling process according to the information. In addition, the present disclosure further discloses a control method of a liquid crystal drop filling system.

Abstract: The invention discloses array substrate, manufacturing method thereof, display panel and display device, array substrate comprises TFTs, common electrodes, common electrode lines, data lines and gate lines, each TFT comprises gate, active layer corresponding to the gate, protective layer corresponding to the gate line or gate, and ESL, the active layer and protective layer are provided in the same layer and separated from each other; the ESL is provided with source holes and drain hole corresponding to the active layer, protective hole corresponding to the protective layer but not overlapping with the data line, and connecting holes corresponding to the common electrode and common electrode line; and distance between each connecting hole and the protective hole closest thereto is smaller than that between the connecting hole and the source or drain hole closest thereto, and/or, diameter of said protective hole is smaller than those of the source and drain holes.