Abstract: Disclosed is an integrated sealed micro-mesh nebulization module, which includes: an nebulization device and a nozzle mechanism disposed on the nebulization device, the nozzle mechanism disposed on the nebulization device is detachably connected with the nebulization device; the nebulization module comprises an annular base, a lower shell disposed in the annular base, an upper shell disposed on the lower shell, a micro-mesh nebulization sheet disposed on the lower shell, a first sealing ring and a second sealing ring respectively disposed on both sides of the micro-mesh nebulization sheet, and a metal contact disposed between the lower shell and the upper shell, with one end connected with the micro-mesh nebulization sheet through a wire, and the other end extending to an exterior of the lower shell and connected with an external driving circuit.

Abstract: A plasma-exclusion-zone ring for a substrate processing system that is configured to process a substrate includes a ring-shaped body, an upper portion of the ring-shaped body, a base and a plasma-exclusion-zone ring notch. The upper portion of the ring-shaped body defines a radially inner surface and a top surface. The base of the ring-shaped body defines a radially outer surface, a first bottom surface extending radially inward from the radially outer surface, and a second bottom surface extending radially inward from the first bottom surface. The plasma-exclusion-zone ring notch is proportional to an alignment notch of the substrate. The first bottom surface is tapered and extends at an acute angle from the second bottom surface to the radially outer surface. The first bottom surface is configured to extend over and oppose a periphery of the substrate.

Abstract: Semiconductor processing methods and apparatuses are provided. Some methods include providing a first wafer to a processing chamber, the first wafer having a thickness, a beveled edge, a first side, and a plurality of devices formed in a device area on the first side, the device area having an outer perimeter, depositing an annular ring of material on the first wafer, the annular ring of material covering a region of the beveled edge and the outer perimeter of the device area, and having an inner boundary closer to the center point of the first wafer than the outer perimeter, bonding a second substrate to the plurality of devices and to a portion of the annular ring of material, and thinning the thickness of the first wafer.

Abstract: Methods and systems for processing a bevel edge of a wafer in a bevel plasma chamber. The method includes receiving a pulsed mode setting for a RF generator of the bevel plasma chamber. The method includes identifying a duty cycle for the pulsed mode, the duty cycle defining an ON time and an OFF time during each cycle of power delivered by the generator. The method includes calculating or accessing a compensation factor to an input RF power setting of the generator. The compensation factor is configured to add an incremental amount of power to the input power setting to account for a loss in power attributed to the duty cycle to be run in the pulsed mode. The method is configured to run the generator in the pulse mode with the duty cycle and the pulsing frequency.

Abstract: Methods for surface interface engineering in semiconductor fabrication are provided herein. In some embodiments, a method of processing a substrate disposed atop a substrate support in a processing volume of a processing chamber includes: generating an ion species from an inductively coupled plasma formed within the processing volume of the processing chamber from a first process gas; exposing a first layer of the substrate to the ion species to form an ammonium fluoride (NH4F) film atop the first layer, wherein the first layer comprises silicon oxide; and heating the substrate to a second temperature at which the ammonium fluoride film reacts with the first layer to selectively etch the silicon oxide.

Abstract: Methods for surface interface engineering in semiconductor fabrication are provided herein. In some embodiments, a method of processing a substrate disposed atop a substrate support in a processing volume of a processing chamber includes: generating an ion species from an inductively coupled plasma formed within the processing volume of the processing chamber from a first process gas; exposing a first layer of the substrate to the ion species to form an ammonium fluoride (NH4F) film atop the first layer, wherein the first layer comprises silicon oxide; and heating the substrate to a second temperature at which the ammonium fluoride film reacts with the first layer to selectively etch the silicon oxide.

Abstract: A structure for a semiconductor device is disclosed. The structure includes a first feature and a second feature. The first feature and the second feature are formed simultaneously in a single etch process from a same monolithic substrate layer and are integrally and continuously connected to each other. The first feature has a width dimension of less than a minimum feature size achievable by lithography and the second feature has a width dimension of at least equal to a minimum feature size achievable by lithography.

Abstract: In an embodiment, a method of fabricating a transistor device comprises: providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers; anisotropically etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate; oxidizing exposed surfaces of the substrate in the recessed regions to form an oxide thereon; removing the oxide from bottoms of the recessed regions while retaining the oxide upon sidewalls of the recessed regions; and isotropically etching the substrate such that the recessed regions undercut the pair of dielectric spacers.

Abstract: Disclosed are embodiments of a method of forming, on an SOI wafer, a planar FET with embedded and faceted source/drain stressors. The method incorporates a directional ion implant process to create amorphous regions at the bottom surfaces of source/drain recesses in a single crystalline semiconductor layer of an SOI wafer. Then, an etch process selective to different crystalline planes over others and further selective to single crystalline semiconductor material over amorphous semiconductor material can be performed in order to selectively adjust the shape (i.e., the profile) of the recess sidewalls without increasing the depth of the recesses. Subsequently, an anneal process can be performed to re-crystallize the amorphous regions and an epitaxial deposition process can be used to fill the recesses with source/drain stressor material. Also disclosed are embodiments of a planar FET structure and a design structure for the planar FET.

Abstract: A transistor device includes a gate conductor spaced above a semiconductor substrate by a gate dielectric, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the channel region comprises undercut areas under the gate conductor; a stressed material embedded in the undercut areas of the channel region under the gate conductor; and epitaxially grown source and drain regions disposed in the recessed regions of the semiconductor substrate laterally adjacent to the stressed material.

Abstract: A method for fabrication of features for an integrated circuit includes patterning a mandrel layer to include structures having a plurality of different widths on a surface of an integrated circuit device. Exposed sidewalls of the structures are reacted to integrally form a new compound in the sidewalls such that the new compound extends into the exposed sidewalls by a controlled amount to form pillars. One or more layers below the pillars are etched using the pillars as an etch mask to form features for an integrated circuit device.

Abstract: A method for fabrication of features for an integrated circuit includes patterning a mandrel layer to include structures having at least one width on a surface of an integrated circuit device. Exposed sidewalls of the structures are reacted to integrally form a new compound in the sidewalls such that the new compound extends into the exposed sidewalls by a controlled amount to form pillars. One or more layers below the pillars are etched using the pillars as an etch mask to form features for an integrated circuit device.

Abstract: A structure for a semiconductor device is disclosed. The structure includes a first feature and a second feature. The first feature and the second feature are formed simultaneously in a single etch process from a same monolithic substrate layer and are integrally and continuously connected to each other. The first feature has a width dimension of less than a minimum feature size achievable by lithography and the second feature has a width dimension of at least equal to a minimum feature size achievable by lithography.

Abstract: Stress enhanced transistor devices and methods of fabricating the same are disclosed. In one embodiment, a transistor device comprises: a gate conductor spaced above a semiconductor substrate by a gate dielectric, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the channel region comprises undercut areas under the gate conductor; a stressed material embedded in the undercut areas of the channel region under the gate conductor; and epitaxially grown source and drain regions disposed in the recessed regions of the semiconductor substrate laterally adjacent to the stressed material.

Abstract: A transistor device includes a gate conductor spaced above a semiconductor substrate by a gate dielectric, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the channel region comprises undercut areas under the gate conductor; a stressed material embedded in the undercut areas of the channel region under the gate conductor; and epitaxially grown source and drain regions disposed in the recessed regions of the semiconductor substrate laterally adjacent to the stressed material.

Abstract: In an embodiment, a method of fabricating a transistor device comprises: providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers; anisotropically etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate; oxidizing exposed surfaces of the substrate in the recessed regions to form an oxide thereon; removing the oxide from bottoms of the recessed regions while retaining the oxide upon sidewalls of the recessed regions; and isotropically etching the substrate such that the recessed regions undercut the pair of dielectric spacers.

Abstract: In an embodiment, a method of fabricating a transistor device comprises: providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers; anisotropically etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate; oxidizing exposed surfaces of the substrate in the recessed regions to form an oxide thereon; removing the oxide from bottoms of the recessed regions while retaining the oxide upon sidewalls of the recessed regions; and isotropically etching the substrate such that the recessed regions undercut the pair of dielectric spacers.

Abstract: A FinFET is described incorporating at least two fins extending from a common Si containing layer and epitaxial material grown from the common layer and from sidewalls of the fins to introduce strain to the common layer and the fins to increase carrier mobility.

Abstract: Disclosed are embodiments of a method of forming, on an SOI wafer, a planar FET with embedded and faceted source/drain stressors. The method incorporates a directional ion implant process to create amorphous regions at the bottom surfaces of source/drain recesses in a single crystalline semiconductor layer of an SOI wafer. Then, an etch process selective to different crystalline planes over others and further selective to single crystalline semiconductor material over amorphous semiconductor material can be performed in order to selectively adjust the shape (i.e., the profile) of the recess sidewalls without increasing the depth of the recesses. Subsequently, an anneal process can be performed to re-crystallize the amorphous regions and an epitaxial deposition process can be used to fill the recesses with source/drain stressor material. Also disclosed are embodiments of a planar FET structure and a design structure for the planar FET.

Abstract: Disclosed are embodiments of a method of forming, on an SOI wafer, a planar FET with embedded and faceted source/drain stressors. The method incorporates a directional ion implant process to create amorphous regions at the bottom surfaces of source/drain recesses in a single crystalline semiconductor layer of an SOI wafer. Then, an etch process selective to different crystalline planes over others and further selective to single crystalline semiconductor material over amorphous semiconductor material can be performed in order to selectively adjust the shape (i.e., the profile) of the recess sidewalls without increasing the depth of the recesses. Subsequently, an anneal process can be performed to re-crystallize the amorphous regions and an epitaxial deposition process can be used to fill the recesses with source/drain stressor material. Also disclosed are embodiments of a planar FET structure and a design structure for the planar FET.