Abstract: A method for fabrication of features for an integrated circuit includes patterning a mandrel layer to include structures having at least one width on a surface of an integrated circuit device. Exposed sidewalls of the structures are reacted to integrally form a new compound in the sidewalls such that the new compound extends into the exposed sidewalls by a controlled amount to form pillars. One or more layers below the pillars are etched using the pillars as an etch mask to form features for an integrated circuit device.

Abstract: A method, gated device and design structure are presented for providing reduced floating body effect (FBE) while not impacting performance enhancing stress. One method includes forming damage in a portion of a substrate adjacent to a gate; removing a portion of the damaged portion to form a trench, leaving another portion of the damaged portion at least adjacent to a channel region; and substantially filling the trench with a material to form a source/drain region.

Abstract: In a field effect transistor (FET), halo features may be formed by etching into the surface of a silicon layer followed by a step of growing a first epitaxial silicon (epi-Si) layer on the etched silicon layer. Source (S) and drain (D), as well as S/D extension features may similarly be formed by etching an epitaxial silicon layer, then filling with another epitaxial layer. Source and Drain, and extensions, and halo, which are normally formed by diffusion, may be formed as discrete elements by etching and filling (epi-Si). This may provide a shallow, highly activated, abrupt S/D extension, an optimally formed halo and deep S/D diffusion doping, and maximized improvement of channel mobility from the compressive or tensile stress from e-SiGe or e-SiC.

Abstract: In one embodiment, a photoresist is lithographically patterned to form an array of patterned photoresist portions having a pitch near twice a minimum feature size. Fluorine-containing polymer spacers are formed on sidewalls of the patterned photoresist portions. The pattern of the fluorine-containing polymer spacers is transferred into an underlying layer to form a pattern having a sublithographic pitch. In another embodiment, a first pattern in a first photoresist is transferred into a first ARC layer underneath to form first ARC portions. A planarizing second optically dense layer, a second ARC layer, and a second photoresist are applied over the first ARC portions. A second pattern in the second photoresist is transferred into the second ARC layer to form second ARC portions. The combination of the first ARC portions and second ARC portions function as an etch mask to pattern an underlying layer with a composite pattern having a sublithographic pitch.

Abstract: Disclosed are embodiments of a method of forming, on an SOI wafer, a planar FET with embedded and faceted source/drain stressors. The method incorporates a directional ion implant process to create amorphous regions at the bottom surfaces of source/drain recesses in a single crystalline semiconductor layer of an SOI wafer. Then, an etch process selective to different crystalline planes over others and further selective to single crystalline semiconductor material over amorphous semiconductor material can be performed in order to selectively adjust the shape (i.e., the profile) of the recess sidewalls without increasing the depth of the recesses. Subsequently, an anneal process can be performed to re-crystallize the amorphous regions and an epitaxial deposition process can be used to fill the recesses with source/drain stressor material. Also disclosed are embodiments of a planar FET structure and a design structure for the planar FET.

Abstract: Stress enhanced transistor devices and methods of fabricating the same are disclosed. In one embodiment, a transistor device comprises: a gate conductor spaced above a semiconductor substrate by a gate dielectric, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the channel region comprises undercut areas under the gate conductor; a stressed material embedded in the undercut areas of the channel region under the gate conductor; and epitaxially grown source and drain regions disposed in the recessed regions of the semiconductor substrate laterally adjacent to the stressed material.

Abstract: In an embodiment, a method of fabricating a transistor device comprises: providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers; anisotropically etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate; oxidizing exposed surfaces of the substrate in the recessed regions to form an oxide thereon; removing the oxide from bottoms of the recessed regions while retaining the oxide upon sidewalls of the recessed regions; and isotropically etching the substrate such that the recessed regions undercut the pair of dielectric spacers.

Abstract: In one embodiment, a photoresist is lithographically patterned to form an array of patterned photoresist portions having a pitch near twice a minimum feature size. Fluorine-containing polymer spacers are formed on sidewalls of the patterned photoresist portions. The pattern of the fluorine-containing polymer spacers is transferred into an underlying layer to form a pattern having a sublithographic pitch. In another embodiment, a first pattern in a first photoresist is transferred into a first ARC layer underneath to form first ARC portions. A planarizing second optically dense layer, a second ARC layer, and a second photoresist are applied over the first ARC portions. A second pattern in the second photoresist is transferred into the second ARC layer to form second ARC portions. The combination of the first ARC portions and second ARC portions function as an etch mask to pattern an underlying layer with a composite pattern having a sublithographic pitch.

Abstract: A method, gated device and design structure are presented for providing reduced floating body effect (FBE) while not impacting performance enhancing stress. One method includes forming damage in a portion of a substrate adjacent to a gate; removing a portion of the damaged portion to form a trench, leaving another portion of the damaged portion at least adjacent to a channel region; and substantially filling the trench with a material to form a source/drain region.

Abstract: In a field effect transistor (FET), halo features may be formed by etching into the surface of a silicon layer followed by a step of growing a first epitaxial silicon (epi-Si) layer on the etched silicon layer. Source (S) and drain (D), as well as S/D extension features may similarly be formed by etching an epitaxial silicon layer, then filling with another epitaxial layer. Source and Drain, and extensions, and halo, which are normally formed by diffusion, may be formed as discrete elements by etching and filling (epi-Si). This may provide a shallow, highly activated, abrupt S/D extension, an optimally formed halo and deep S/D diffusion doping, and maximized improvement of channel mobility from the compressive or tensile stress from e-SiGe or e-SiC.

Abstract: A plasma processing system includes a source of plasma, a substrate and a shutter positioned in close proximity to the substrate. The substrate/shutter relative disposition is changed for precise control of substrate/plasma interaction. This way, the substrate interacts only with a fully established, stable plasma for short times required for nanoscale processing of materials. The shutter includes an opening of a predetermined width, and preferably is patterned to form an array of slits with dimensions that are smaller than the Debye screening length. This enables control of the substrate/plasma interaction time while avoiding the ion bombardment of the substrate in an undesirable fashion. The relative disposition between the shutter and the substrate can be made either by moving the shutter or by moving the substrate.

Abstract: A plasma processing system includes a source of plasma, a substrate and a shutter positioned in close proximity to the substrate. The substrate/shutter relative disposition is changed for precise control of substrate/plasma interaction. This way, the substrate interacts only with a fully established, stable plasma for short times required for nanoscale processing of materials. The shutter includes an opening of a predetermined width, and preferably is patterned to form an array of slits with dimensions that are smaller than the Debye screening length. This enables control of the substrate/plasma interaction time while avoiding the ion bombardment of the substrate in an undesirable fashion. The relative disposition between the shutter and the substrate can be made either by moving the shutter or by moving the substrate.