Abstract: In one embodiment, a memory interface comprises a cleanup phase-locked loop (PLL) configured to receive a reference clock signal, and to generate a clean clock signal based on the reference clock signal. The memory interface also comprises a synchronization circuit configured to receive data, a data clock signal, and the clean clock signal, wherein the synchronization circuit is further configured to sample the data using the data clock signal, and to synchronize the sampled data with the clean clock signal.

Abstract: Techniques are described that embed a digital assisted regulator with an LDO regulator on a chip without requiring a capacitor external to the chip and to regulate a voltage without undershoot. The digital assisted regulator responds to information regarding operation of the LDO regulator and to a signal that provides advance notification of a load change. When the advance notification signal is received, the digital assisted regulator pulls a circuit's supply voltage up to a chip's incoming supply voltage. When the correct operating voltage has been reached and any undershoot problem removed, the digital assisted regulator balances the current it provides with the current provided by the LDO regulator, to allow a quick response time for other load changes. Also, bandwidth of an LDO regulator may be expanded by use of an advance notice signal to increase bias current of an LDO output device to meet an upcoming load change.

Abstract: A high voltage tolerant differential receiver circuit includes a voltage divider ladder that is operative to divide in half differential input signals that are greater than threshold voltages of the voltage divider ladder. A pass gate circuit is operative to receive differential input signals that are below the threshold voltage of the voltage divider ladder. Outputs from the voltage divider ladder and the pass gate circuit are provided to separate comparators. Output from the comparators are combined to generate a signal in the voltage domain of receiver circuitry.

Abstract: An apparatus for sharing a serial communication port between a plurality of communication channels is described. The apparatus comprises a transceiver that manages communications over the serial communication port. The apparatus also includes a multiplexer coupled to the transceiver, wherein the multiplexer multiplexes the plurality of communication channels. The apparatus also includes identification information circuitry coupled to the multiplexer, wherein the identification information circuitry adds identification information to data from the plurality of communication channels that enables the plurality of communication channels to share the serial communication port. The serial communications port and the multiplexer permit communication between integrated circuits that meet at least one latency metric for the plurality of communication channels when the plurality of communication channels are active.

Abstract: A high voltage tolerant single ended receiver circuit includes a voltage divider that is operative to divide in half single ended input signals that are greater than the threshold voltages of the voltage divider. A pass gate circuit is operative to receive single ended signals that are below the threshold voltages of the voltage divider. Output from the voltage divider is coupled to a first input of a modified Schmitt trigger circuit to control a high threshold level of the Schmitt trigger circuit. Output from the pass gate circuit is coupled to a second input of the modified Schmitt trigger circuit to control a low threshold level of the Schmitt trigger circuit.

Abstract: A high voltage tolerant single ended receiver circuit includes a voltage divider that is operative to divide in half single ended input signals that are greater than the threshold voltages of the voltage divider. A pass gate circuit is operative to receive single ended signals that are below the threshold voltages of the voltage divider. Output from the voltage divider is coupled to a first input of a modified Schmitt trigger circuit to control a high threshold level of the Schmitt trigger circuit. Output from the pass gate circuit is coupled to a second input of the modified Schmitt trigger circuit to control a low threshold level of the Schmitt trigger circuit.

Abstract: A high voltage tolerant differential receiver circuit includes a voltage divider ladder that is operative to divide in half differential input signals that are greater than threshold voltages of the voltage divider ladder. A pass gate circuit is operative to receive differential input signals that are below the threshold voltage of the voltage divider ladder. Outputs from the voltage divider ladder and the pass gate circuit are provided to separate comparators. Output from the comparators are combined to generate a signal in the voltage domain of receiver circuitry.

Abstract: A Delay-Locked Loop (DLL) uses a delay line to delay a first signal by a “delay time”, thereby generating a second signal. A capacitor is charged at a first rate starting at a first edge of first signal and continuing until an edge of the second signal. The capacitor is then discharged at a second rate until another edge of the first signal. A control loop controls the delay time such that the amount the capacitor is charged is the same as the amount the capacitor is discharged. The delay time is constant and is substantially independent of variations in the duty cycle of the first signal. In one example, duty cycle distortion cancellation is accomplished by changing the first rate proportionally with respect to changes in first signal duty cycle. In another example, the first and second rates are independent of the duty cycle of the first signal.

Abstract: A Delay-Locked Loop (DLL) uses a delay line to delay a first signal by a “delay time”, thereby generating a second signal. A capacitor is charged at a first rate starting at a first edge of first signal and continuing until an edge of the second signal. The capacitor is then discharged at a second rate until another edge of the first signal. A control loop controls the delay time such that the amount the capacitor is charged is the same as the amount the capacitor is discharged. The delay time is constant and is substantially independent of variations in the duty cycle of the first signal. In one example, duty cycle distortion cancellation is accomplished by changing the first rate proportionally with respect to changes in first signal duty cycle. In another example, the first and second rates are independent of the duty cycle of the first signal.