Patents by Inventor Y. Mohammed Kasem

Y. Mohammed Kasem has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6538300
    Abstract: A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor.
    Type: Grant
    Filed: September 14, 2000
    Date of Patent: March 25, 2003
    Assignee: Vishay Intertechnology, Inc.
    Inventors: Haim Goldberger, Sik Lui, Jacek Korec, Y. Mohammed Kasem, Harianto Wong, Jack Van Den Heuvel
  • Publication number: 20030030125
    Abstract: A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor.
    Type: Application
    Filed: July 29, 2002
    Publication date: February 13, 2003
    Inventors: Haim Goldberger, Sik Lui, Jacek Korec, Y. Mohammed Kasem, Harianto Wong, Jack Van Den Heuvel
  • Publication number: 20020185710
    Abstract: A semiconductor package by which contacts are made to both sides of the dice is manufactured on a wafer scale. The back side of the wafer is attached to a metal plate. The scribe lines separating the dice are saw cut to expose the metal plate but the cuts do not extend through the metal plate. A metal layer, which may include a number of sublayers, is formed on the front side of the dice, the metal covering the exposed portions of the metal plate and extending the side edges of the dice. Separate sections of the metal layer may also cover connection pads on the front side of the dice. A second set of saw cuts are made coincident with the first set of saw cuts, using a blade that is narrower than the blade used to make the first set of saw cuts. As a result, the metal layer remains on the side edges of the dice connecting the back and front sides of the dice (via the metal plate).
    Type: Application
    Filed: May 28, 2002
    Publication date: December 12, 2002
    Applicant: Vishay Intertechnology, Inc.
    Inventors: Felix Zandman, Y. Mohammed Kasem, Yueh-Se Ho
  • Patent number: 6441475
    Abstract: This semiconductor surface mount package is relatively inexpensive to produce and has a footprint that is essentially the same size as the die. A conductive substrate is attached to the back side of a wafer and is in electrical contact with a terminal on the back side of each die in the wafer. A nonconductive overcoat is formed and patterned on the front side of the wafer, leaving a portion of the passivation layer and the connection pads for the dice exposed, each of the connection pads being coated with a solderable metal layer. The assembly is then sawed in perpendicular directions along the scribe lines between the dice, but the saw cuts do not extend all the way through the substrate, which remains intact at its back side. The parallel cuts in one direction are broken to produce die strips which are mounted, sandwich-like, in a stack, with one side of the strips exposed.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: August 27, 2002
    Assignee: Vishay Intertechnology, Inc.
    Inventors: Felix Zandman, Y. Mohammed Kasem, Yueh-Se Ho
  • Patent number: 6392290
    Abstract: In a semiconductor package for a chip having terminals on both sides, for example, a power MOSFET in which the gate and source terminals are on the front side and the drain terminal is on the back side, electrical contact is made with the back side terminal by extending vias, which can take the form of trenches, holes or other cavities, either entirely or patrially through the chip. The vias are filled with a metal or other electrically conductive material. The process is performed on the chips in a wafer simultaneously. The resulting package is compact and economical to manufacture and can readily be mounted, flip-chip style, on a printed circuit board.
    Type: Grant
    Filed: April 7, 2000
    Date of Patent: May 21, 2002
    Assignee: Siliconix Incorporated
    Inventors: Y. Mohammed Kasem, Yueh-Se Ho, Lee Shawn Luo, Chang-Sheng Chen, Eddy Tjhia, Bosco Lan, Jacek Korec, Anup Bhalla
  • Patent number: 6316287
    Abstract: A package for a semiconductor device is formed by a process which includes forming a metal layer in contact with a connection pad on the front side of a semiconductor die while the die is still a part of a wafer. The metal layer extends into the scribe line between the die and an adjacent die. A nonconductive cap is attached to the front side of the wafer, and the wafer is ground from its back side to reduce its thickness. A cut is made from the back side of the wafer, preferably by sawing and etching, to expose the metal layer. A nonconductive layer is formed on the back side of the wafer and a second metal layer is deposited over the nonconductive layer, the second metal layer extending into the scribe line where it makes contact with the first metal layer through an opening in the nonconductive layer. Preferably, a solder post is formed on the second metal layer to allow the finished package to be mounted on a printed circuit board.
    Type: Grant
    Filed: September 13, 1999
    Date of Patent: November 13, 2001
    Assignee: Vishay Intertechnology, Inc.
    Inventors: Felix Zandman, Y. Mohammed Kasem, Yueh-Se Ho
  • Publication number: 20010016369
    Abstract: A semiconductor package by which contacts are made to both sides of the dice is manufactured on a wafer scale. The back side of the wafer is attached to a metal plate. The scribe lines separating the dice are saw cut to expose the metal plate but the cuts do not extend through the metal plate. A metal layer, which may include a number of sublayers, is formed on the front side of the dice, the metal covering the exposed portions of the metal plate and extending the side edges of the dice. Separate sections of the metal layer may also cover connection pads on the front side of the dice. A second set of saw cuts are made coincident with the first set of saw cuts, using a blade that is narrower than the blade used to make the first set of saw cuts. As a result, the metal layer remains on the side edges of the dice connecting the back and front sides of the dice (via the metal plate).
    Type: Application
    Filed: April 26, 2001
    Publication date: August 23, 2001
    Inventors: Felix Zandman, Y. Mohammed Kasem, Yueh-Se Ho
  • Patent number: 6271060
    Abstract: This semiconductor surface mount package is relatively inexpensive to produce and has a footprint that is essentially the same size as the die. A conductive substrate is attached to the back side of a wafer and is in electrical contact with a terminal on the back side of each die in the wafer. A nonconductive overcoat is formed and patterned on the front side of the wafer, leaving a portion of the passivation layer and the connection pads for the dice exposed, each of the connection pads being coated with a solderable metal layer. The assembly is then sawed in perpendicular directions along the scribe lines between the dice, but the saw cuts do not extend all the way through the substrate, which remains intact at its back side. The parallel cuts in one direction are broken to produce die strips which are mounted, sandwich-like, in a stack, with one side of the strips exposed.
    Type: Grant
    Filed: September 13, 1999
    Date of Patent: August 7, 2001
    Assignee: Vishay Intertechnology, Inc.
    Inventors: Felix Zandman, Y. Mohammed Kasem, Yueh-Se Ho
  • Publication number: 20010009298
    Abstract: A package for a semiconductor device is formed by a process which includes forming a metal layer in contact with a connection pad on the front side of a semiconductor die while the die is still a part of a wafer. The metal layer extends into the scribe line between the die and an adjacent die. A nonconductive cap is attached to the front side of the wafer, and the wafer is ground from its back side to reduce its thickness. A cut is made from the back side of the wafer, preferably by sawing and etching, to expose the metal layer. A nonconductive layer is formed on the back side of the wafer and a second metal layer is deposited over the nonconductive layer, the second metal layer extending into the scribe line where it makes contact with the first metal layer through an opening in the nonconductive layer. Preferably, a solder post is formed on the second metal layer to allow the finished package to be mounted on a printed circuit board.
    Type: Application
    Filed: February 23, 2001
    Publication date: July 26, 2001
    Inventors: Felix Zandman, Y. Mohammed Kasem, Yueh-Se Ho
  • Patent number: 6249041
    Abstract: An improved semiconductor device is disclosed. In one embodiment, the semiconductor device includes a semiconductor chip with contact areas on the top or bottom surface. A first lead assembly, formed from a semi-rigid sheet of conductive material, has a lead assembly contact attached to one of the contact areas of the semiconductor chip. The first lead assembly also has at least one lead connected to and extending from the lead assembly contact. A second lead assembly, also formed from a semi-rigid sheet of conductive material, has a lead assembly contact attached to another one of the contact areas of the semiconductor chip. The second lead assembly also has at least one lead connected to and extending from the lead assembly contact. An encapsulant encloses the semiconductor chip, the lead assembly contact of the first lead assembly and the lead assembly contact of the second lead assembly.
    Type: Grant
    Filed: June 2, 1998
    Date of Patent: June 19, 2001
    Assignee: Siliconix Incorporated
    Inventors: Y. Mohammed Kasem, Anthony C. Tsui, Lixiong Luo, Yueh-Se Ho
  • Publication number: 20010000631
    Abstract: This semiconductor surface mount package is relatively inexpensive to produce and has a footprint that is essentially the same size as the die. A conductive substrate is attached to the back side of a wafer and is in electrical contact with a terminal on the back side of each die in the wafer. A nonconductive overcoat is formed and patterned on the front side of the wafer, leaving a portion of the passivation layer and the connection pads for the dice exposed, each of the connection pads being coated with a solderable metal layer. The assembly is then sawed in perpendicular directions along the scribe lines between the dice, but the saw cuts do not extend all the way through the substrate, which remains intact at its back side. The parallel cuts in one direction are broken to produce die strips which are mounted, sandwich-like, in a stack, with one side of the strips exposed.
    Type: Application
    Filed: December 8, 2000
    Publication date: May 3, 2001
    Inventors: Felix Zandman, Y. Mohammed Kasem, Yueh-Se Ho
  • Patent number: 6066890
    Abstract: A multiple integrated circuit intra-package configuration having a centrally mounted integrated circuit die and an additional circuit device mounted in the package periphery. The additional circuit device may provide multiple functions, for example, to protect and enhance the performance of the integrated circuit die. Examples of such functions are electrostatic discharge protection circuits and temperature sensing. The intra-package circuit device avoids problems such as simple and complex process compatibility and additional space requirements of utilizing components external to the package. The multiple circuit intra-package configuration utilizes the small space available in the vicinity of lead posts in integrated circuit packages such as SOIC and TSSOP configurations to mount circuit devices. In one embodiment, a circuit device, for example, a diode, is mounted on a lead post and connected as desired using any of a variety of connectability alternatives such as wire bonding.
    Type: Grant
    Filed: November 13, 1995
    Date of Patent: May 23, 2000
    Assignee: Siliconix incorporated
    Inventors: Anthony C. Tsui, Y. Mohammed Kasem