Abstract: The present invention relates to assays and kits for carrying out said assays for the rapid, automated detection of infectious pathogenic agents and normal and abnormal genes. The present invention further relates to methods for general amplification of genomic DNA and total mRNAs and for analyzing differential mRNA expression using the amplification methods disclosed herein.

Abstract: It has now been found that certain novel N-(substituted aryl)-4-(disubstituted methyl)piperidine and pyridine derivatives have provided unexpected insecticidal activity. These compounds are represented by formula (I): wherein m, n, q, r, and s are independently selected from 0 or 1; and p is 0, 1, 2, or 3; A is C or CH; and B, D, E, R, R1, R2, R3, R4, R5, R6, R7 and R8 are fully described herein. In addition, compositions comprising an insecticidally effective amount of at least one compound of formula I, and optionally, an effective amount of at least one of a second compound, with at least one insecticidally compatible carrier are also disclosed; along with methods of controlling insects comprising applying said compositions to a locus where insects are present or are expected to be present.

Abstract: A chopper-stabilized amplifier receiving an input signal includes a first operational transconductance amplifier having an input chopper and an output chopper for chopping an output signal produced by the first operational transconductance amplifier. A switched capacitor notch filter filters the chopped output signal by operating synchronously with the chopping frequency of output chopper to filter ripple voltages that otherwise would be produced by the output chopper. In one embodiment, a second operational transconductance amplifier amplifies the notch filter output. The input signal is fed forward, summed with the output of the second operational transconductance amplifier, and applied to the input of a fourth operational transconductance amplifier. Ripple noise and offset are substantially reduced.

Abstract: An amplifier has a wide bandwidth and a high gain by using parallel loads. Each load has a load resistor and a load p-channel transistor in parallel. The drain voltages of differential n-channel transistors can be set by the load resistors, while switching current is provided by the load p-channel transistors. The parallel load provides a high impedance to the drain nodes yet still provides driving current. A transconductance stage with a pair of differential transistors and two parallel loads drives a shunt-shunt-feedback stage that has another pair of differential transistors and two more parallel loads. Shunt resistors between the gate and drain of the differential transistors in the shunt-shunt-feedback stage provide shunt feedback and low impedance. Several pairs of transconductance and shunt-shunt-feedback stages can be cascaded together. The cascaded amplifier may be used as a signal repeater.

Abstract: An improved method and circuit for reduced settling time in an amplifier are provided. The amplifier comprises a composite amplifier circuit including a first amplifier configured with a second amplifier comprising an integrator circuit. The reduced settling time is facilitated through implementation of a faster path configured between an inverting input terminal of the second amplifier and an output terminal of the first amplifier for current needed by an integrator resistor due to any signal appearing at said inverting input terminal for said high-speed amplifier. The faster path can be realized through the addition of a compensation capacitor between the output terminal of the composite amplifier circuit and the inverting input terminal of the second amplifier. The compensation capacitor can comprise various values depending on any given number of design criteria.

Abstract: Certain novel phenyl substituted cyclic derivatives have unexpected insecticidal activity. These compounds are represented by formula I: where B is a cyclic bridging group containing at least one N or N oxide link and a, A, b, B, c, d, D, L, M, R1 through R9, inclusively, and R13, R14 and R15 are fully described herein. In addition, novel intermediates useful in preparing compounds of Formula I, compositions comprising an insecticidally effective amount of at least one compound of formula I, and optionally, an effective amount of at least one of a second compound, with at least one insecticidally compatible carrier are also disclosed; along with methods of controlling insects comprising applying said compositions to a locus where insects are present or are expected to be present.

Abstract: Apparatus and methods are disclosed herein that provide reduced bus transaction latency on a bus architecture that includes at least one master coupled to a plurality of slaves. As disclosed herein, a device (e.g., a slave) may include bus logic and host logic coupled to the bus logic. The bus logic may obtain a serialization token permitting the host logic to complete a transaction received by the bus logic via the bus. Further, the bus logic may keep the serialization token to complete at least one other transaction.

Abstract: Certain novel (dihalopropenyl)phenylalkyl substituted benzodioxolane and benzodioxane derivatives have provided unexpected insecticidal activity. These compounds are represented by formula I: where R through R10, inclusively, x, A, B, y, D, E, G and M are fully described herein. Preferred compounds of the present invention are those wherein the benzofused ring moiety is attached to the remainder of the molecule at the positions designated as 1- or 2-. In addition, compositions comprising an insecticidally effective amount of at least one compound of formula I, and optionally, an effective amount of at least one of a second compound, with at least one insecticidally compatible carrier are also disclosed; along with methods of controlling insects comprising applying said compositions to a locus where insects are present or are expected to be present.

Abstract: It has now been found that certain novel N-(substituted aryl)-4-(disubstituted methyl)piperidine and pyridine derivatives have provided unexpected insecticidal activity. These compounds are represented by formula (I): wherein m, n, q, r, and s are independently selected from 0 or 1; and p is 0, 1, 2, or 3; A is CH or N; and B, D, E, R, R1, R2, R3, R4, R5, R6, R7 and R8 are fully described herein. In addition, compositions comprising an insecticidally effective amount of at least one compound of formula I, and optionally, an effective amount of at least one of a second compound, with at least one insecticidally compatible carrier are also disclosed; along with methods of controlling insects comprising applying said compositions to a locus where insects are present or are expected to be present.

Abstract: The invention provides a cache management system comprising in various embodiments pre-load and pre-own functionality to enhance cache efficiency in shared memory distributed cache multiprocessor computer systems. Some embodiments of the invention comprise an invalidation history table to record the line addresses of cache lines invalidated through dirty or clean invalidation, and which is used such that invalidated cache lines recorded in an invalidation history table are reloaded into cache by monitoring the bus for cache line addresses of cache lines recorded in the invalidation history table. In some further embodiments, a write-back bit associated with each L2 cache entry records when either a hit to the same line in another processor is detected or when the same line is invalidated in another processor's cache, and the system broadcasts write-backs from the selected local cache only when the line being written back has a write-back bit that has been set.

Abstract: A frequency-multiplying circuit generates a multiple of the fundamental frequency of a crystal that oscillates. A first differential multiplier is coupled to the crystal nodes and generates a frequency-doubled output. The frequency-doubled output is applied to an op amp that buffers the output and compares it to a reference to generate a pair of differential buffered signals. The differential buffered signals are applied to a second differential multiplier that generates a final quadrupled-frequency output. The differential multipliers can each have a pair of differential transistors that receive signals that oscillate out-of-phase to each other by 180 degrees. The drains of the differential transistors connect together at a summing node to sum the transistor currents, producing the frequency-doubled output. A crystal driver circuit using cross-coupled and direct-coupled transistors may also be attached to the crystal nodes.

Abstract: An output stage circuit is configured for enabling an output of an amplifier circuit to be pulled upwards and/or downwards to or beyond an upper power supply or below a lower power supply. The exemplary output stage circuit comprises a pair of output transistors configured to provide an output voltage, and a controlled resistive circuit. The controlled resistive element is configured to enhance the gain of the output stage circuit by modifying the dynamic impedance effect of the upper output transistor during pull-up operation, or the lower output transistor during pull-down operation. During normal operation, the controlled resistive element operates with low resistance, e.g., acts as a “short,” but during the pull-up or pull-down operation the controlled resistive element can be configured to add resistance to modify the dynamic impedance of the upper or lower output transistor.

Abstract: Insecticidal (dihalopropenyl) phenylalkyl substituted dihydrobenzofuran and dihydrobenzopyran derivatives of Formula I are disclosed. These compounds provide unexpected insecticidal activity across a spectrum of insect pests combined with desirable physical properties including improved photostability. wherein x and y are integers independently selected from 0 or 1; and B is a bridging group *—(CR16R17)q—(CR18R19)r—(CR20R21)s-Lt-(CR22R23)u—(CR24R25)v—(CR26R27)w—, where the asterisk denotes attachment at A; and q, r, s, u, v and w are integers independently selected from 0, 1 and 2; and t is an integer selected from 0 and 1. A, D, E, G, M, R through R11, and R16 through R27, inclusively, are fully described herein. In addition, compositions comprising an insecticidally effective amount of at least one compound of formula I and methods of controlling insects by applying said compositions to a locus where insects are present or are expected to be present are also disclosed.

Abstract: A voltage-controlled oscillator (VCO) for a phase-locked loop (PLL) has improved bandwidth and performance at lower frequency. A variable current source supplies a current to an internal oscillator-power node. The current varies with the VCO input voltage. The internal oscillator-power node drives the sources of p-channel transistors in inverter stages in the ring oscillator. The variable current causes the internal oscillator-power node's voltage to vary, which varies the output frequency. An active resistor is in parallel with the ring oscillator. The active resistor has a resistor and an n-channel transistor in series between the oscillator-power node and ground. The n-channel transistor has a fixed bias voltage on its gate and is non-linear. The non-linear effective resistance of the n-channel transistor improves overall linearity of the ring oscillator. The parallel effective resistance of the active resistor lowers overall effective resistance of the ring oscillator.

Abstract: This invention is a cache memory employing a tag bypass controller to detect a memory access to the same cache line as a last cache miss address and a last cache hit address. This information is uses for efficient data accesses and forwarding. Registers store the last miss-address and the last hit-address and corresponding valid flags. These hardware features allow reduced tag-RAM accesses and greatly reduce the latency required to fully re-stock a missed cache line.

Abstract: A method and circuit for providing a faster overload recovery time for an amplifier circuit is provided. An overload recovery circuit is configured to reduce and/or eliminate the slow tail voltage that may be caused by overloading a composite amplifier, and thus provide a faster overload recovery time over a wide range of feedback components for the composite amplifier. The overload recovery circuit comprises a bypass device configured to provide a path for additional current to flow through during overload conditions, thus creating a “clamping” action with the feedback element of the amplifier circuit. As a result, the current flowing through the bypass device of the amplifier circuit will be large enough to hold an inverting node of the composite amplifier at the common mode voltage, thus reducing the overload recovery time.

Abstract: An improved method allowing for rapid sensitive and standardized detection of a target nucleic acid from a pathogenic microorganism or virus or normal or abnormal gene in a sample is provided. The method involves hybridizing a target nucleic acid to several non-overlapping oligonucleotide probes that hybridize to adjacent regions in the target nucleic acid, the probes being referred to capture/amplification probes and amplification probes, respectively, in the presence of paramagnetic beads coated with a ligand binding moiety. Through the binding of a ligand attached to one end of the capture/amplification probe and the specific hybridization of portions of the probes to adjacent sequences in the target nucleic acid, a complex comprising the target nucleic acid, the probes and the paramagnetic beads is formed. The probes may then ligated together to form a contiguous ligated amplification sequence bound to the beads, which complex may be denatured to remove the target nucleic acid and unligated probes.

Abstract: The invention provides a cache management system comprising in various embodiments pre-load and pre-own functionality to enhance cache efficiency in shared memory distributed cache multiprocessor computer systems. Some embodiments of the invention comprise an invalidation history table to record the line addresses of cache lines invalidated through dirty or clean invalidation, and which is used such that invalidated cache lines recorded in an invalidation history table are reloaded into cache by monitoring the bus for cache line addresses of cache lines recorded in the invalidation history table. In some further embodiments, a write-back bit associated with each L2 cache entry records when either a hit to the same line in another processor is detected or when the same line is invalidated in another processor's cache, and the system broadcasts write-backs from the selected local cache only when the line being written back has a write-back bit that has been set.

Abstract: Apparatus and methods are disclosed herein that provide reduced bus transaction latency on a bus architecture that includes at least one master coupled to a plurality of slaves. As disclosed herein, a device (e.g., a slave) may include bus logic and host logic coupled to the bus logic. The bus logic may obtain a serialization token permitting the host logic to complete a transaction received by the bus logic via the bus. Further, the bus logic may keep the serialization token to complete at least one other transaction.

Abstract: The present invention relates to assays and kits for carrying out said assays for the rapid, automated detection of infectious pathogenic agents and normal and abnormal genes. The present invention further relates to methods for general amplification of genomic DNA and total mRNAs and for analyzing differential mRNA expression using the amplification methods disclosed herein.