Patents by Inventor Ya-Chen Kao
Ya-Chen Kao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230221465Abstract: A display device includes a display module and an anti-glare film on the display module. The anti-glare film includes a first anti-glare layer and a second anti-glare layer. The first anti-glare layer has a plurality of microstructures at an upper surface of the first anti-glare layer. A root-mean-square slope of the microstructures is more than 0 and is 0.2 or less. The second anti-glare layer is between the first anti-glare layer and the display module, and an inner haze of the second anti-glare layer is from 20% to 90%.Type: ApplicationFiled: August 9, 2022Publication date: July 13, 2023Inventors: Shu-Cheng KUNG, Ya-Chen KAO, Ken-Yu LIU
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Patent number: 11672124Abstract: The present disclosure relates to an integrated circuit that includes a semiconductor substrate having a periphery region and memory cell region separated by a boundary region. A pair of split gate flash memory cells are disposed on the memory cell region and include a first select gate and a first memory gate. A first gate electrode is disposed over a first gate dielectric layer on the periphery region. A second gate electrode is disposed over a second gate dielectric layer on the periphery region at a position between the boundary region and the first gate electrode. The second dielectric layer is thicker than the first gate dielectric layer. The first select gate and the first memory gate have upper surfaces that are co-planar or level with the upper surface of the second gate electrode.Type: GrantFiled: February 25, 2021Date of Patent: June 6, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Ya-Chen Kao, Yi Hsien Lu
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Patent number: 11600618Abstract: A includes depositing a gate electrode layer over a semiconductor substrate; patterning the gate electrode layer into a first gate electrode and a gate electrode extending portion; forming a first gate spacer alongside the first gate electrode; patterning the gate electrode extending portion into a second gate electrode after forming the first gate spacer; and forming a second gate spacer alongside the second gate electrode and a third gate spacer around the first spacer.Type: GrantFiled: March 18, 2021Date of Patent: March 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Harry-Hak-Lay Chuang, Li-Feng Teng, Wei-Cheng Wu, Fang-Lan Chu, Ya-Chen Kao
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Publication number: 20220302114Abstract: A includes depositing a gate electrode layer over a semiconductor substrate; patterning the gate electrode layer into a first gate electrode and a gate electrode extending portion; forming a first gate spacer alongside the first gate electrode; patterning the gate electrode extending portion into a second gate electrode after forming the first gate spacer; and forming a second gate spacer alongside the second gate electrode and a third gate spacer around the first spacer.Type: ApplicationFiled: March 18, 2021Publication date: September 22, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Harry-Hak-Lay CHUANG, Li-Feng TENG, Wei-Cheng WU, Fang-Lan CHU, Ya-Chen KAO
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Patent number: 11264292Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.Type: GrantFiled: November 13, 2019Date of Patent: March 1, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Han Lin, Chih-Ren Hsieh, Ya-Chen Kao, Chen-Chin Liu, Chih-Pin Huang
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Patent number: 11257816Abstract: A semiconductor device includes active gate structures and dummy gate electrodes. The active gate structures are above an active region of a substrate. The dummy gate electrodes are above the active region of the substrate. A number of the dummy gate electrodes is less than a number of the active gate structures. The active gate structures and the dummy gate electrodes have different materials, and a distance between adjacent one of the dummy gate electrodes and one of the active gate structures is substantially the same as a gate pitch of the active gate structures.Type: GrantFiled: February 18, 2020Date of Patent: February 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Harry-Hak-Lay Chuang, Wei-Cheng Wu, Ya-Chen Kao
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Patent number: 11088040Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.Type: GrantFiled: September 21, 2019Date of Patent: August 10, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Han Lin, Chih-Ren Hsieh, Ya-Chen Kao, Chen-Chin Liu, Chih-Pin Huang
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Patent number: 11063058Abstract: A memory device includes a semiconductor substrate, a select gate stack, a main gate, a charge trapping layer, and a spacer. The a select gate stack is over the semiconductor substrate. The main gate is over the semiconductor substrate. The charge trapping layer has a first portion between the main gate and the semiconductor substrate. The spacer is on a sidewall of the main gate. At least a portion of the main gate is between the spacer and the select gate stack, and a lowermost surface of the spacer is above a lowermost surface of the main gate.Type: GrantFiled: May 15, 2020Date of Patent: July 13, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Harry-Hak-Lay Chuang, Wei-Cheng Wu, Ya-Chen Kao
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Publication number: 20210183880Abstract: The present disclosure relates to an integrated circuit that includes a semiconductor substrate having a periphery region and memory cell region separated by a boundary region. A pair of split gate flash memory cells are disposed on the memory cell region and include a first select gate and a first memory gate. A first gate electrode is disposed over a first gate dielectric layer on the periphery region. A second gate electrode is disposed over a second gate dielectric layer on the periphery region at a position between the boundary region and the first gate electrode. The second dielectric layer is thicker than the first gate dielectric layer. The first select gate and the first memory gate have upper surfaces that are co-planar or level with the upper surface of the second gate electrode.Type: ApplicationFiled: February 25, 2021Publication date: June 17, 2021Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Ya-Chen Kao, Yi Hsien Lu
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Patent number: 10971544Abstract: Methods for forming a magneto-resistive memory device and a capacitor in an interconnect structure are disclosed herein. An exemplary method includes forming a first level interconnect metal layer and a second level interconnect metal layer of an interconnect structure. The method further includes simultaneously forming a first plurality of layers in a first region of the interconnect structure and a second plurality of layers in a second region of the interconnect structure, wherein the first plurality of layers and the second plurality of layers are disposed between the first level interconnect metal layer and the second level interconnect metal layer. The first plurality of layers is configured as a magneto-resistive memory device. The second plurality of layers is configured as the capacitor. The magneto-resistive memory device and the capacitor are each coupled to the first level interconnect metal layer and the second level interconnect metal layer.Type: GrantFiled: July 25, 2018Date of Patent: April 6, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTDInventors: Chung-Cheng Chou, Ya-Chen Kao, Tien-Wei Chiang
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Patent number: 10957704Abstract: The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-? metal gate) integrated circuit which includes a high-voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.Type: GrantFiled: January 6, 2020Date of Patent: March 23, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Ya-Chen Kao, Yi Hsien Lu
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Publication number: 20210057409Abstract: A semiconductor device includes active gate structures and dummy gate electrodes. The active gate structures are above an active region of a substrate. The dummy gate electrodes are above the active region of the substrate. A number of the dummy gate electrodes is less than a number of the active gate structures. The active gate structures and the dummy gate electrodes have different materials, and a distance between adjacent one of the dummy gate electrodes and one of the active gate structures is substantially the same as a gate pitch of the active gate structures.Type: ApplicationFiled: February 18, 2020Publication date: February 25, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Harry-Hak-Lay CHUANG, Wei-Cheng WU, Ya-Chen KAO
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Patent number: 10827154Abstract: A display device of the present invention includes a light source apparatus and a rear light transmitting module disposed opposite a first light emitting surface of the light source apparatus. The rear light transmitting module includes a first transmitting layer and a second transmitting layer. The first transmitting layer has a plurality of first prisms arranged side by side and respectively protruding toward the first light emitting surface. The second transmitting layer is overlapped with the first transmitting layer on one side thereof opposite the first light emitting surface, and has a plurality of second prisms arranged side by side and respectively protruding toward the first transmitting layer. A vertical projection range of the first prisms on the first light emitting surface is misaligned with a vertical projection range of the second prisms on the first light emitting surface.Type: GrantFiled: May 15, 2019Date of Patent: November 3, 2020Assignee: AU OPTRONICS CORPORATIONInventors: Jui-Sheng Wu, Tsai-Fen Wu, Ya-Chen Kao
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Publication number: 20200279857Abstract: A memory device includes a semiconductor substrate, a select gate stack, a main gate, a charge trapping layer, and a spacer. The a select gate stack is over the semiconductor substrate. The main gate is over the semiconductor substrate. The charge trapping layer has a first portion between the main gate and the semiconductor substrate. The spacer is on a sidewall of the main gate. At least a portion of the main gate is between the spacer and the select gate stack, and a lowermost surface of the spacer is above a lowermost surface of the main gate.Type: ApplicationFiled: May 15, 2020Publication date: September 3, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Harry-Hak-Lay CHUANG, Wei-Cheng WU, Ya-Chen KAO
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Patent number: 10658373Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a split gate stack having a main gate and a select gate and forming a logic gate stack having a logic gate over a semiconductor substrate. The main gate and the logic gate is respectively replaced with a metal memory gate and a metal logic gate, in which the main gate and the logic gate are replaced simultaneously.Type: GrantFiled: August 6, 2018Date of Patent: May 19, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Harry-Hak-Lay Chuang, Wei-Cheng Wu, Ya-Chen Kao
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Publication number: 20200144279Abstract: The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-? metal gate) integrated circuit which includes a high-voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.Type: ApplicationFiled: January 6, 2020Publication date: May 7, 2020Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Ya-Chen Kao, Yi Hsien Lu
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Publication number: 20200083126Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.Type: ApplicationFiled: November 13, 2019Publication date: March 12, 2020Inventors: Meng-Han Lin, Chih-Ren Hsieh, Ya-Chen Kao, Chen-Chin Liu, Chih-Pin Huang
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Publication number: 20200020601Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.Type: ApplicationFiled: September 21, 2019Publication date: January 16, 2020Inventors: Meng-Han Lin, Chih-Ren Hsieh, Ya-Chen Kao, Chen-Chin Liu, Chih-Pin Huang
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Patent number: 10535574Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.Type: GrantFiled: April 25, 2018Date of Patent: January 14, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Meng-Han Lin, Chih-Ren Hsieh, Ya-Chen Kao, Chen-Chin Liu, Chih-Pin Huang
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Patent number: 10535675Abstract: The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-? metal gate) integrated circuit which includes a high-voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.Type: GrantFiled: April 29, 2019Date of Patent: January 14, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Ya-Chen Kao, Yi Hsien Lu