Patents by Inventor Ya-Chen Kao
Ya-Chen Kao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20140141533Abstract: One method includes forming an anti-ferromagnetic layer on a substrate. A ferromagnetic layer may be formed on the anti-ferromagnetic layer. The ferromagnetic layer includes a first, second and third portions where the second portion is located between the first and third portions. A first ion irradiation is performed to only one portion of the ferromagnetic layer. A second ion irradiation is performed to another portion of the ferromagnetic layer.Type: ApplicationFiled: January 31, 2014Publication date: May 22, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Huang Lai, Sheng-Huang Huang, Kuo-Feng Huang, Ming-Te Liu, Chun-Jung Lin, Ya-Chen Kao, Wen-Cheng Chen
-
Patent number: 8648401Abstract: A semiconductor memory device includes a first ferromagnetic layer magnetically pinned and positioned within a first region of a substrate; a second ferromagnetic layer approximate the first ferromagnetic layer; and a barrier layer interposed between the first ferromagnetic layer and the first portion of the second ferromagnetic layer. The second ferromagnetic layer includes a first portion being magnetically free and positioned within the first region; a second portion magnetically pinned to a first direction and positioned within a second region of the substrate, the second region contacting the first region from a first side; and a third portion magnetically pinned to a second direction and positioned within a third region of the substrate, the third region contacting the first region from a second side.Type: GrantFiled: September 17, 2010Date of Patent: February 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Huang Lai, Sheng-Huang Huang, Kuo-Feng Huang, Ming-Te Liu, Chun-Jung Lin, Ya-Chen Kao, Wen-Cheng Chen
-
Patent number: 8629518Abstract: A magnetic tunnel junction (MTJ) etching process uses a sacrifice layer. An MTJ cell structure includes an MTJ stack with a first magnetic layer, a second magnetic layer, and a tunnel barrier layer in between the first magnetic layer and the second magnetic layer, and a sacrifice layer adjacent to the second magnetic layer, where the sacrifice layer protects the second magnetic layer in the MTJ stack from oxidation during an ashing process. The sacrifice layer does not increase a resistance of the MTJ stack. The sacrifice layer can be made of Mg, Cr, V, Mn, Ti, Zr, Zn, or any alloy combination thereof, or any other suitable material. The sacrifice layer can be multi-layered and/or have a thickness ranging from 5 ? to 400 ?. The MTJ cell structure can have a top conducting layer over the sacrifice layer.Type: GrantFiled: July 1, 2010Date of Patent: January 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Jen Wang, Ya-Chen Kao, Chun-Jung Lin
-
Patent number: 8570792Abstract: A magnetoresistive random access memory (MRAM) cell includes a magnetic tunnel junction (MTJ), a top electrode disposed over the MTJ, a bottom electrode disposed below the MTJ, and an induction line disposed above or below the MTJ. The induction line is configured to induce a magnetic field at the MTJ.Type: GrantFiled: January 24, 2012Date of Patent: October 29, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tien-Wei Chiang, Kai-Chun Lin, Ya-Chen Kao, Hung-Chang Yu
-
Publication number: 20130200475Abstract: A magnetoresistive random access memory (MRAM) device and a method of manufacture are provided. The MRAM device comprises a magnetic pinned layer, a compound GMR structure acting as a free layer, and a non-magnetic barrier layer separating the pinned and GMR layers. The barrier layer is provided to reduce the magnetic coupling of the free layer and GMR structure, as well as provide a resistive state (high or low) for retaining binary data (0 or 1) in the device. The GMR structure provides physical electrode connectivity for set/clear memory functionality which is separated from the physical electrode connectivity for the read functionality for the memory device.Type: ApplicationFiled: February 2, 2012Publication date: August 8, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tien-Wei Chiang, Chwen Yu, Ya-Chen Kao
-
Publication number: 20130188418Abstract: A magnetoresistive random access memory (MRAM) cell includes a magnetic tunnel junction (MTJ), a top electrode disposed over the MTJ, a bottom electrode disposed below the MTJ, and an induction line disposed above or below the MTJ. The induction line is configured to induce a magnetic field at the MTJ.Type: ApplicationFiled: January 24, 2012Publication date: July 25, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tien-Wei CHIANG, Kai-Chun LIN, Ya-Chen KAO, Hung-Chang YU
-
Publication number: 20130155759Abstract: Test structures, methods of manufacturing thereof, test methods, and magnetic random access memory (MRAM) arrays are disclosed. In one embodiment, a test structure is disclosed. The test structure includes an MRAM cell having a magnetic tunnel junction (MTJ) and a transistor coupled to the MTJ. The test structure includes a test node coupled between the MTJ and the transistor, and a contact pad coupled to the test node.Type: ApplicationFiled: December 16, 2011Publication date: June 20, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ya-Chen Kao, Tien-Wei Chiang, Chun-Jung Lin
-
Patent number: 8450722Abstract: A magnetoresistive random access memory (MRAM) cell includes a magnetic tunnel junction (MTJ), a top electrode disposed over the MTJ, a bottom electrode disposed below the MTJ, and an induction line disposed to one side of the MTJ. The induction line is configured to induce a perpendicular magnetic field at the MTJ.Type: GrantFiled: July 15, 2011Date of Patent: May 28, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Te Liu, Tien-Wei Chiang, Ya-Chen Kao, Wen-Cheng Chen
-
Patent number: 8416600Abstract: Apparatus and methods are disclosed herein for a reverse-connection STT MTJ element of a MRAM to overcome the source degeneration effect when switching the magnetization of the MTJ element from the parallel to the anti-parallel direction. A memory cell of a MRAM having a reverse-connection MTJ element includes a switching device having a source, a gate, and a drain, and a reverse-connection MTJ device having a free layer, a fixed layer, and an insulator layer interposed between the free layer and the fixed layer. The free layer of the reverse-connection MTJ device is connected to the drain of the switching device and the fixed layer is connected to a bit line (BL). The reverse-connection MTJ device applies the lower IMTJ capability of the memory cell caused by the source degeneration effect to the less stringent IMTJ(AP->P) while preserving the higher IMTJ capability for the more demanding IMTJ(P->AP).Type: GrantFiled: November 25, 2009Date of Patent: April 9, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Jung Lin, Yu-Jen Wang, Ya-Chen Kao, Wen-Cheng Chen, Ming-Te Liu
-
Publication number: 20130075839Abstract: The present disclosure provides a MTJ stack for an MRAM device. The MTJ stack includes a pinned ferromagnetic layer over a pinning layer; a tunneling barrier layer over the pinned ferromagnetic layer; a free ferromagnetic layer over the tunneling barrier layer; a conductive oxide layer over the free ferromagnetic layer; and a oxygen-based cap layer over the conductive oxide layer.Type: ApplicationFiled: September 24, 2011Publication date: March 28, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Ming Chen, Ya-Chen Kao, Ming-Te Liu, Chung-Yi Yu, Cheng-Yuan Tsai, Chun-Jung Lin
-
Publication number: 20130038418Abstract: A communications structure comprises a first semiconductor substrate having a first coil, and a second semiconductor substrate having a second coil above the first semiconductor substrate. Inner edges of the first and second coils define a boundary of a volume that extends below the first coil and above the second coil. A ferromagnetic core is positioned at least partially within the boundary, such that a mutual inductance is provided between the first and second coils for wireless transmission of signals or power between the first and second coils.Type: ApplicationFiled: August 10, 2011Publication date: February 14, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ping-Lin Yang, Jun-De Jin, Fu-Lung Hsueh, Sa-Lly Liu, Tong-Chern Ong, Chun-Jung Lin, Ya-Chen Kao
-
Publication number: 20130015538Abstract: A magnetoresistive random access memory (MRAM) cell includes a magnetic tunnel junction (MTJ), a top electrode disposed over the MTJ, a bottom electrode disposed below the MTJ, and an induction line disposed to one side of the MTJ. The induction line is configured to induce a perpendicular magnetic field at the MIJ.Type: ApplicationFiled: July 15, 2011Publication date: January 17, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Te LIU, Tien-Wei CHIANG, Ya-Chen KAO, Wen-Cheng CHEN
-
Publication number: 20120068279Abstract: A semiconductor memory device includes a first ferromagnetic layer magnetically pinned and positioned within a first region of a substrate; a second ferromagnetic layer approximate the first ferromagnetic layer; and a barrier layer interposed between the first ferromagnetic layer and the first portion of the second ferromagnetic layer. The second ferromagnetic layer includes a first portion being magnetically free and positioned within the first region; a second portion magnetically pinned to a first direction and positioned within a second region of the substrate, the second region contacting the first region from a first side; and a third portion magnetically pinned to a second direction and positioned within a third region of the substrate, the third region contacting the first region from a second side.Type: ApplicationFiled: September 17, 2010Publication date: March 22, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Huang Lai, Sheng-Huang Huang, Kuo-Feng Huang, Ming-Te Liu, Chun-Jung Lin, Ya-Chen Kao, Wen-Cheng Chen
-
Patent number: 8110881Abstract: A MRAM cell structure includes a bottom electrode; a magnetic tunnel junction unit disposed on the bottom electrode; a top electrode disposed on the magnetic tunnel junction unit; and a blocking layer disposed on the top electrode, wherein the blocking layer is wider than the magnetic tunnel junction unit for preventing against formation of a short circuit between a contact and the magnetic tunnel junction unit.Type: GrantFiled: September 27, 2007Date of Patent: February 7, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ya-Chen Kao, Chun-Jung Lin, Yu-Jen Wang, Hsu-Chen Cheng, Feng-Jia Shiu, Yung-Tao Lin
-
Patent number: 7951670Abstract: A split gate memory cell. A floating gate is disposed on and insulated from a substrate comprising an active area separated by a pair of isolation structures formed therein. The floating gate is disposed between the pair of isolation structures and does not overlap the upper surface thereof. A cap layer is disposed on the floating gate. A control gate is disposed over the sidewall of the floating gate and insulated therefrom, partially extending to the upper surface of the cap layer. A source region is formed in the substrate near one side of the floating gate.Type: GrantFiled: March 6, 2006Date of Patent: May 31, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Ming Huang, Hung-Cheng Sung, Wen-Ting Chu, Chang-Jen Hsieh, Ya-Chen Kao
-
Publication number: 20110122674Abstract: Apparatus and methods are disclosed herein for a reverse-connection STT MTJ element of a MRAM to overcome the source degeneration effect when switching the magnetization of the MTJ element from the parallel to the anti-parallel direction. A memory cell of a MRAM having a reverse-connection MTJ element includes a switching device having a source, a gate, and a drain, and a reverse-connection MTJ device having a free layer, a fixed layer, and an insulator layer interposed between the free layer and the fixed layer. The free layer of the reverse-connection MTJ device is connected to the drain of the switching device and the fixed layer is connected to a bit line (BL). The reverse-connection MTJ device applies the lower IMTJ capability of the memory cell caused by the source degeneration effect to the less stringent IMTJ(AP->P) while preserving the higher IMTJ capability for the more demanding IMTJ(P->AP).Type: ApplicationFiled: November 25, 2009Publication date: May 26, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: CHUN-JUNG LIN, Yu-Jen Wang, Ya-Chen Kao, Wen-Cheng Chen, Ming-Te Liu
-
Publication number: 20110001201Abstract: A magnetic tunnel junction (MTJ) etching process uses a sacrifice layer. An MTJ cell structure includes an MTJ stack with a first magnetic layer, a second magnetic layer, and a tunnel barrier layer in between the first magnetic layer and the second magnetic layer, and a sacrifice layer adjacent to the second magnetic layer, where the sacrifice layer protects the second magnetic layer in the MTJ stack from oxidation during an ashing process. The sacrifice layer does not increase a resistance of the MTJ stack. The sacrifice layer can be made of Mg, Cr, V, Mn, Ti, Zr, Zn, or any alloy combination thereof, or any other suitable material. The sacrifice layer can be multi-layered and/or have a thickness ranging from 5 ? to 400 ?. The MTJ cell structure can have a top conducting layer over the sacrifice layer.Type: ApplicationFiled: July 1, 2010Publication date: January 6, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Jen WANG, Ya-Chen KAO, Chun-Jung LIN
-
Patent number: 7834410Abstract: The present disclosure provides a semiconductor memory device. The device includes a bottom electrode over a semiconductor substrate; an anti-ferromagnetic layer disposed over the bottom electrode; a pinned layer disposed over the anti-ferromagnetic layer; a barrier layer disposed over the pinned layer; a first ferromagnetic layer disposed over the barrier layer; a buffer layer disposed over the first ferromagnetic layer, the buffer layer including tantalum; a second ferromagnetic layer disposed over the buffer layer; and a top electrode disposed over the second ferromagnetic layer.Type: GrantFiled: April 13, 2009Date of Patent: November 16, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Jen Wang, Ya-Chen Kao, Chun-Jung Lin
-
Publication number: 20100258886Abstract: The present disclosure provides a semiconductor memory device. The device includes a bottom electrode over a semiconductor substrate; an anti-ferromagnetic layer disposed over the bottom electrode; a pinned layer disposed over the anti-ferromagnetic layer; a barrier layer disposed over the pinned layer; a first ferromagnetic layer disposed over the barrier layer; a buffer layer disposed over the first ferromagnetic layer, the buffer layer including tantalum; a second ferromagnetic layer disposed over the buffer layer; and a top electrode disposed over the second ferromagnetic layer.Type: ApplicationFiled: April 13, 2009Publication date: October 14, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Jen Wang, Ya-Chen Kao, Chun-Jung Lin
-
Patent number: 7683447Abstract: A method for fabricating a magnetoresistive random access memory (MRAM) device having a plurality of memory cells includes: forming a fixed magnetic layer having magnetic moments fixed in a predetermined direction; forming a tunnel layer over the fixed magnetic layer; forming a free magnetic layer, having magnetic moments aligned in a direction that is adjustable by applying an electromagnetic field, over the tunnel layer; forming a hard mask on the free magnetic layer partially covering the free magnetic layer; and unmagnetizing portions of the free magnetic layer uncovered by the hard mask for defining one or more magnetic tunnel junction (MTJ) units.Type: GrantFiled: September 12, 2007Date of Patent: March 23, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Jen Wang, Young-Shying Chen, Ya-Chen Kao, Chun-Jung Lin