Abstract: A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 ?m. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.

Abstract: A method includes providing a substrate having a surface such that a first hard mask layer is formed over the surface and a second hard mask layer is formed over the first hard mask layer, forming a first pattern in the second hard mask layer, where the first pattern includes a first mandrel oriented lengthwise in a first direction and a second mandrel oriented lengthwise in a second direction different from the first direction, and where the first mandrel has a top surface, a first sidewall, and a second sidewall opposite to the first sidewall, and depositing a material towards the first mandrel and the second mandrel such that a layer of the material is formed on the top surface and the first sidewall but not the second sidewall of the first mandrel.

Abstract: A magnetoresistive random access memory (MRAM) structure, including a substrate and multiple MRAM cells on the substrate, wherein the MRAM cells are arranged in a memory region adjacent to a logic region. An ultra low-k (ULK) layer covers the MRAM cells, wherein the surface portion of ultra low-k layer is doped with fluorine, and dents are formed on the surface of ultra low-k layer at the boundaries between the memory region and the logic region.

Abstract: The present invention relates to a method for preparing etelcalcetide hydrochloride (etelcalcetide HCL). A first peptide is de-protected and cleaved from a solid support by a first solution system, for obtaining a second peptide, followed by coupling an activated L-Cys-OH to the second peptide in the second solution system for forming a TFA salt of etelcalcetide that is not or hardly dissolved in the second solution system. After purification by column chromatography, the TFA salt of etelcalcetide can be converted to etelcalcetide HCL using a third solution system that excludes hydrogen chloride during a real-time monitoring salt exchange step. The present method provides a simplified process and the etelcalcetide HCL with high purity and yield, for being advantageously applied in mass production of etelcalcetide HCL.

Abstract: A power-on reset signal generating apparatus and a voltage detection circuit thereof are provided. The voltage detection circuit includes a latch circuit, a pre-charge circuit, a pull-down switch and an output stage circuit. The pull-down circuit is turned on or cut off according to the power-on reset signal. The pre-charge circuit operates a pre-charge action according to a power-on reset signal or a power supply voltage. The output stage circuit receives the power supply voltage, based on the power supply voltage, generates a detection output voltage according to an input end of the inverter and the power-on reset signal.

Abstract: A display panel includes a first substrate, an upper capacitor electrode, a capacitor dielectric layer, a second substrate opposite to the first substrate, a conductive bump, an electroluminescent layer, and a counter electrode. The upper capacitor electrode is disposed on an inner surface of the second substrate. The upper capacitor electrode is disposed on an inner surface of the second substrate. The capacitor dielectric layer covers the upper capacitor electrode of the second substrate. The first substrate has at least one pixel electrode and a first capacitor electrode separated from the pixel electrode. The conductive bump is protrusively disposed on the first capacitor electrode of the first substrate. The electroluminescent layer is sandwiched between the pixel electrode and the counter electrode.

Abstract: A display panel includes a substrate, a conductive bump, a capacitor dielectric layer, a sensing electrode, a counter substrate opposite to the substrate, an electroluminescent layer, and a counter electrode. The conductive bump protrudes from an inner surface of the substrate and includes an upper capacitor electrode and a bump covered by the upper capacitor electrode. The bump is disposed between the inner surface of the substrate and the upper capacitor electrode. The capacitor dielectric layer covers the conductive bump and a portion of the inner surface of the substrate. The sensing electrode is disposed on the inner surface of the substrate or an inner surface of the counter substrate. The counter substrate has at least one pixel electrode and a first capacitor electrode separated from the pixel electrode. The electroluminescent layer is disposed between the pixel electrode and the counter electrode.

Abstract: Disclosed herein is a quantum rod backlight module for a liquid crystal display. The quantum rod backlight module includes a quantum rod layer disposing at one side of a backlight source and comprising a plurality of quantum rods, wherein the major axes of the plurality of quantum rods are aligned along a direction parallel to a surface of the quantum rod layer; a first micro-prism layer including a plurality of first parallel strip-shape prisms, and a second micro-prism layer including a plurality of second parallel strip-shape prisms, wherein both of the alignment directions of the first parallel strip-shape prisms and the second parallel strip-shape prisms are perpendicular to the direction of the major axes of the plurality of quantum rods, and the retardations of the first micro-prism layer and the second micro-prism layer are zero.

Abstract: A display panel includes a first substrate, an upper capacitor electrode, a capacitor dielectric layer, a second substrate opposite to the first substrate, a conductive bump, an electroluminescent layer, and a counter electrode. The upper capacitor electrode is disposed on an inner surface of the second substrate. The upper capacitor electrode is disposed on an inner surface of the second substrate. The capacitor dielectric layer covers the upper capacitor electrode of the second substrate. The first substrate has at least one pixel electrode and a first capacitor electrode separated from the pixel electrode. The conductive bump is protrusively disposed on the first capacitor electrode of the first substrate. The electroluminescent layer is sandwiched between the pixel electrode and the counter electrode.

Abstract: A display panel includes a substrate, a conductive bump, a capacitor dielectric layer, a sensing electrode, a counter substrate opposite to the substrate, an electroluminescent layer, and a counter electrode. The conductive bump protrudes from an inner surface of the substrate and includes an upper capacitor electrode and a bump covered by the upper capacitor electrode. The bump is disposed between the inner surface of the substrate and the upper capacitor electrode. The capacitor dielectric layer covers the conductive bump and a portion of the inner surface of the substrate. The sensing electrode is disposed on the inner surface of the substrate or an inner surface of the counter substrate. The counter substrate has at least one pixel electrode and a first capacitor electrode separated from the pixel electrode. The electroluminescent layer is disposed between the pixel electrode and the counter electrode.

Abstract: A biological test sheet includes an insulating substrate, an electrode structure, a first insulating septum and an insulating layer. The electrode structure is disposed on the insulating substrate and has at least one top surface and at least one side surface, and the side surface is connected between at least one fringe of the top surface and the insulating substrate. The first insulating septum is disposed on the insulating substrate and partially covers the electrode structure. The first insulating septum has a notch, and the notch exposes a first segment of the electrode structure. The insulating layer covers the fringe of the top surface and the side surface at the first segment of the electrode structure.

Abstract: Disclosed herein is a quantum rod backlight module for a liquid crystal display. The quantum rod backlight module includes a quantum rod layer disposing at one side of a backlight source and comprising a plurality of quantum rods, wherein the major axes of the plurality of quantum rods are aligned along a direction parallel to a surface of the quantum rod layer; a first micro-prism layer including a plurality of first parallel strip-shape prisms, and a second micro-prism layer including a plurality of second parallel strip-shape prisms, wherein both of the alignment directions of the first parallel strip-shape prisms and the second parallel strip-shape prisms are perpendicular to the direction of the major axes of the plurality of quantum rods, and the retardations of the first micro-prism layer and the second micro-prism layer are zero.

Abstract: A juicer comprises a base. A motor electrically connected to a controller disposed inside the base. The controller controls an axis of the motor to turn clockwise or anti-clockwise. The axis of the motor has a first end and a second end in an opposite direction to the first end. The first end of the axis is axially connected with a first unidirectional bearing coupled with a first connecting element coaxially. The second end of the axis is axially connected with a second unidirectional bearing coupled with a second connecting element coaxially. The second connecting element is moved together with a third connecting element. Thereby, the axis of the motor turns in clockwise or anti-clockwise direction for selectively enabling the first connecting element to move upwardly together with a first cutter inside a first container and to turn the first cutter for cutting.

Abstract: A cover of a processor for fruits and vegetables is connected above a cutter. The cover comprises a cover body and a container. The cover body has a feed tube. The feed tube has an accommodating space running through vertically. A first positioning element is disposed on an outer circumference of the feed tube. The cover body having a water inlet hole through which the accommodating space is in communication with an outside of the cover body. A second positioning element correspondingly connected with the first positioning element disposed on a side of the container, so that the container and the feed tube are connected with each other. A water outlet end is disposed at a bottom of the container for correspondingly being communication with the water inlet hole; thereby, water in the container flows from the water outlet end into the accommodating space through the water inlet hole.

Abstract: A serial interface flash memory apparatus and a writing method for a status register thereof are disclosed. The writing method for the status register mentioned above includes: receiving a write command with an updated data for the status register; writing the updated data to a volatile latch and set an update flag according to whether or not a write-protected data in the status register is updated by the write command; and writing the data from the volatile latch to the status register according to the update flag when a power down process of the serial interface flash memory apparatus is processed.

Abstract: A serial interface flash memory apparatus and a writing method for a status register thereof are disclosed. The writing method for the status register mentioned above includes: receiving a write command with an updated data for the status register; writing the updated data to a volatile latch and set an update flag according to whether or not a write-protected data in the status register is updated by the write command; and writing the data from the volatile latch to the status register according to the update flag when a power down process of the serial interface flash memory apparatus is processed.

Abstract: An inverted pendulum type moving body. The inverted pendulum type moving body includes: a vehicle body having a riding part on which a rider rides; a rotary body which is rotatably supported on the vehicle body; a rotary body drive unit which rotatably drives the rotary body; and a control device which controls the rotary body drive unit for allowing the inverted pendulum type moving body to travel in accordance with a traveling instruction while keeping a balance, wherein the inverted pendulum type moving body further includes an uncontrollable state detection unit for detecting a state where the control of the inverted pendulum type moving body by the rider is highly improbable, and the control device stops a traveling of the inverted pendulum type moving body when the uncontrollable state is detected based on information detected by the uncontrollable state detection unit.

Abstract: A semiconductor memory and address-decoding circuit and method for decoding address allow the semiconductor memory to operate under a decreased capacity by disabling or hiding a predetermined portion of the semiconductor memory. The semiconductor memory has a first address-inputting circuit configured to receive a first external address, a switching circuit configured to switch a predetermined portion of the first external address to form an internal address, at least one address-setting code configured to set at least one predetermined bit of the internal address, a decoder coupling to the switching circuit and the address-setting code, and a memory array coupling to the decoder, wherein the decoder is configured to select at least one memory unit of the memory array based on the internal address. The first address-inputting circuit, the switching circuit and the address-setting code can be considered as an address-decoding circuit.

Abstract: The inventions provides a method for identifying a target virus in an infected subject comprising the steps of designing a pair of degenerate primers corresponding to highly conserved regions of the target virus; designing a pair of species-specific primers according to highly variable sequences within the conserved regions of the target virus; preparing the species-specific probes according to the larger sequence variations within the conserved regions of the target virus, which are amplified with the species-specific primers as obtained; preparing a test sample by amplifying total nucleic acid of the infected subject with the degenerate primers as obtained; contacting the test sample with the species-specific probes as obtained; and detecting a hybridization between the species-specific probe and the test sample, wherein the hybridization indicates the target virus is identified in the infected subject. The primers and probes for detecting a garget virus are also provided.

Abstract: A semiconductor memory and address-decoding circuit and method for decoding address allow the semiconductor memory to operate under a decreased capacity by disabling or hiding a predetermined portion of the semiconductor memory. The semiconductor memory comprises a first address-inputting circuit configured to receive a first external address, a switching circuit configured to switch a predetermined portion of the first external address to form an internal address, at least one address-setting code configured to set at least one predetermined bit of the internal address, a decoder coupling to the switching circuit and the address-setting code, and a memory array coupling to the decoder, wherein the decoder is configured to select at least one memory unit of the memory array based on the internal address. The first address-inputting circuit, the switching circuit and the address-setting code can be considered as an address-decoding circuit.