Abstract: A semiconductor memory and address-decoding circuit and method for decoding address allow the semiconductor memory to operate under a decreased capacity by disabling or hiding a predetermined portion of the semiconductor memory. The semiconductor memory comprises a first address-inputting circuit configured to receive a first external address, a switching circuit configured to switch a predetermined portion of the first external address to form an internal address, at least one address-setting code configured to set at least one predetermined bit of the internal address, a decoder coupling to the switching circuit and the address-setting code, and a memory array coupling to the decoder, wherein the decoder is configured to select at least one memory unit of the memory array based on the internal address. The first address-inputting circuit, the switching circuit and the address-setting code can be considered as an address-decoding circuit.

Abstract: The inventions provides a method for identifying a target virus in an infected subject comprising the steps of designing a pair of degenerate primers corresponding to highly conserved regions of the target virus; designing a pair of species-specific primers according to highly variable sequences within the conserved regions of the target virus; preparing the species-specific probes according to the larger sequence variations within the conserved regions of the target virus, which are amplified with the species-specific primers as obtained; preparing a test sample by amplifying total nucleic acid of the infected subject with the degenerate primers as obtained; contacting the test sample with the species-specific probes as obtained; and detecting a hybridization between the species-specific probe and the test sample, wherein the hybridization indicates the target virus is identified in the infected subject. The primers and probes for detecting a garget virus are also provided.

Abstract: A semiconductor memory array and method for use in a memory device in which the location of a memory cell in the array is specified by row address and column address decoders. The memory cells may be floating gate memory cells in which data is programmed by hot carrier injection and erased by Fowler-Nordheim tunneling. The array includes bit lines connected to the column address decoder, and word lines and N+ diffusion source lines connected to the row address decoder. Each memory cell has a gate connected to a word line, a drain connected to a bit line and a source connected to the N+ diffusion source line. A low resistance source line formed of metal II or other conductive material is arranged adjacent to each N+ source line and is electrically connected thereto at one or more locations via interconnecting straps. The low resistance source lines serve to reduce the voltage drop across the N+ diffusion source lines during program operations and provide an improved ground connection during read operations.