Abstract: A method of forming a stressed thin film on a substrate includes forming a plurality of islands on a viscous layer that is present on a surface of a substrate. Adjacent islands are bridged with a stressor layer. The structure is annealed at an elevated temperature above the glass flow temperature of the viscous layer to transfer at least a portion of the stress from the stressor layer to the underlying islands. The bridges are then removed to expose the stressed islands of thin film on the substrate.

Abstract: A method for controlling dislocation position in a silicon germanium buffer layer located on a substrate includes depositing a strained silicon germanium layer on the substrate and irradiating one or more regions of the silicon germanium layer with a dislocation inducing agent. The dislocation inducing agent may include ions, electrons, or other radiation source. Dislocations in the silicon germanium layer are located in one or more of the regions. The substrate and strained silicon germanium layer may then be subjected to an annealing process to transform the strained silicon germanium layer into a relaxed state. A top layer of strained silicon or silicon germanium may be deposited on the relaxed silicon germanium layer. Semiconductor-based devices may then be fabricated in the non-damaged regions of the strained silicon or silicon germanium layer. Threading dislocations are confined to damaged areas which may be transformed into SiO2 isolation regions.

Abstract: An article of manufacture includes a substrate, a relaxed buffer layer disposed on the substrate, and a plurality of isolation regions formed in the relaxed buffer layer. The isolation regions include threading dislocations while the remainder of the relaxed buffer layer is substantially free of threading dislocations. The relaxed buffer layer may be formed from silicon germanium while the substrate may be formed from silicon. A capping layer may be disposed over the relaxed buffer layer.

Abstract: A method of forming an optically active region on a silicon substrate includes the steps of epitaxially growing a silicon buffer layer on the silicon substrate and epitaxially growing a SiGe cladding layer having a plurality of arrays of quantum dots disposed therein, the quantum dots being formed from a compound semiconductor material having a lattice mismatch with the silicon buffer layer. The optically active region may be incorporated into devices such as light emitting diodes, laser diodes, and photodetectors.

Abstract: An isolation region for use in a semiconductor device is formed in a p-type silicon substrate. An n-type silicon layer is disposed on the p-type silicon substrate, wherein the n-type silicon layer is separated by an oxidized porous silicon layer. At least a portion of the oxidized porous silicon layer is recessed below the n-type silicon layer. The isolation region may be formed between neighboring semiconductor devices such as, for example, transistors.

Abstract: A method for forming dislocation-free strained silicon thin film includes the step of providing two curved silicon substrates. One substrate is curved by the presence of silicon dioxide on a back surface. The other substrate is curved by the presence of a silicon nitride layer. One of the substrates is subject to hydrogen implantation and the two substrates are bonded to one another in an annealing process. The two substrates are separated, thereby leaving a layer of strained silicon on a front side of one of the substrates. A back side layer of silicon dioxide or silicon nitride is then removed to restore the substrate to a substantially planar state. The method may be employed to form dislocation-free strained silicon thin films. The films may be under tensile or compressive strain.

Abstract: A method of depositing conformal film into high aspect ratio spaces includes the step of forming a gradient of precursor gas inside the space(s) prior to deposition. The gradient may be formed, for example, by reducing the pressure within the deposition chamber or by partial evacuation of the deposition chamber. The temperature of the substrate is then briefly increased to preferentially deposit precursor material within the closed or “deep” portion of the high aspect ratio space. The process may be repeated for a number of cycles to completely fill the space(s). The process permits the filling of high aspect ratio spaces without any voids or keyholes that may adversely impact the performance of the resulting device.

Abstract: An integrated circuit laminate with a metal substrate for use with high performance mixed signal integrated circuit applications. The metal substrate provides substantially improved crosstalk isolation, enhanced heat sinking and an easy access to a true low impedance ground. In one embodiment, the metal layer has regions with insulation filled channels or voids and a layer of insulator such as unoxidized porous silicon disposed between the metal substrate and a silicon integrated circuit layer. The laminate also has a plurality of metal walls or trenches mounted to the metal substrate and transacting the silicon and insulation layers thereby isolating noise sensitive elements from noise producing elements on the chip. In another embodiment, the laminate is mounted to a flexible base to limit the flexion of the chip.

Abstract: A method of forming a self-assembled film with periodic nanometer dimension features (e.g., holes) on a substrate includes the steps of providing film precursors on the substrate, wherein the film precursors are maintained in an amorphous state. Where the film precursors are block copolymers, a heating member is provided. The substrate and the heating member are then moved relative to one another so as to raise the temperature of a portion of the film precursor on the substrate above its glass transition temperature. Relative movement between the substrate and heating member continues until a self-assembled crystalline film is formed over the surface of the substrate. In an alternative embodiment, a pH dispensing member is provided to dispense a pH adjusting agent onto the substrate that promotes self-assembly of a crystalline film.

Abstract: A method of forming shallow trenches used, for example, in shallow trench isolation includes the steps of providing a p-type silicon substrate, forming a layer in the p-type silicon substrate, wherein the layer includes p-type silicon interposed between n-type silicon. The p-type silicon layer interposed between the n-type silicon is then subject to an anodization process to form porous silicon. The porous silicon regions are then oxidized. The porosity of the silicon layer may be controlled to create an isolation region that is either substantially flush with, above, or below an upper surface of the n-type top layer. For example, by adjusting the anodization time, a retrograde cross-sectional profile of the shallow trench can be obtained that leads to improved isolation between adjacent devices.

Abstract: A method, structure and article of manufacture related to hetero-integration of dissimilar semiconductor materials. A mask is created on a semiconductor substrate, wherein the mask includes one or more openings, and each of the openings includes one or more overhangs. The overhangs cover a hetero-epitaxial interface region between a film expitaxially grown on the substrate and the substrate itself, thereby preventing a “line-of-sight” view along a surface norm of the substrate in the hetero-epitaxial interface region between the epitaxial film and the substrate. There is only one hetero-epitaxial interface region for each of the openings, which results in only one epitaxial growth front coalescence per opening, thereby reducing the number of highly defective regions from epitaxial growth front coalescence by a factor of two.

Abstract: Methods of fabricating highly conductive regions in semiconductor substrates for radio frequency applications are used to fabricate two structures: (1) a first structure includes porous Si (silicon) regions extending throughout the thickness of an Si substrate that allows for the subsequent formation of metallized posts and metallized moats in the porous regions; and (2) a second structure includes staggered deep V-grooves or trenches etched into an Si substrate, or some other semiconductor substrate, from the front and/or the back of the substrate, wherein these V-grooves and trenches are filled or coated with metal to form the metallized moats.

Abstract: A method, structure and article of manufacture related to hetero-integration of dissimilar semiconductor materials. A mask is created on a semiconductor substrate, wherein the mask includes one or more openings, and each of the openings includes one or more overhangs. The overhangs cover a hetero-epitaxial interface region between a film expitaxially grown on the substrate and the substrate itself, thereby preventing a “line-of-sight” view along a surface norm of the substrate in the hetero-epitaxial interface region between the epitaxial film and the substrate. There is only one hetero-epitaxial interface region for each of the openings, which results in only one epitaxial growth front coalescence per opening, thereby reducing the number of highly defective regions from epitaxial growth front coalescence by a factor of two.

Abstract: A method, structure and article of manufacture related to hetero-integration of dissimilar semiconductor materials. A mask is created on a semiconductor substrate, wherein the mask includes one or more openings, and each of the openings includes one or more overhangs. The overhangs cover a hetero-epitaxial interface region between a film expitaxially grown on the substrate and the substrate itself, thereby preventing a “line-of-sight” view along a surface norm of the substrate in the hetero-epitaxial interface region between the epitaxial film and the substrate. There is only one hetero-epitaxial interface region for each of the openings, which results in only one epitaxial growth front coalescence per opening, thereby reducing the number of highly defective regions from epitaxial growth front coalescence by a factor of two.

Abstract: An integrated circuit with a buried layer for increasing the Q of an inductor formed in the integrated circuit. The substrate includes a highly doped buried preserving device and latchup characteristics. The inductor may also include an increased thickness conductive layer in the inductor to further increase Q. The present invention is also directed to a low loss interconnect.

Abstract: An optical device that is a waveguide with a heating element thereon that is formed on a silicon substrate is disclosed. The waveguide is formed on a region of porous silicon formed in the silicon substrate. The porous silicon region provides greater resistance to the flow of heat than the silicon substrate on which the device is formed. Optionally, the porous silicon region also provides greater resistance to the flow of heat than the waveguide.

Abstract: A process for fabricating a silica-based optical device on a silicon substrate is disclosed. The device has a cladding formed in a silicon substrate. The device also has an active region, and that active region is formed on the cladding. The cladding is fabricated by forming a region of porous silicon in the silicon substrate. The porous silicon is then oxidized and densified. After densification, the active region of the device is formed on the cladding.

Abstract: A process for device fabrication in which transient enhanced diffusion (TED) is used to obtain a desired distribution of dopants in a crystalline substrate is disclosed. In the process, at least two dopants and a non-dopant are introduced into the same region of a substrate. The diffusion of the dopants in the substrate during a subsequent thermal anneal is affected by the non-dopant. The amount of non-dopant introduced into the substrate is selected to obtain, in conjunction with the subsequent thermal anneal, the desired distribution of dopants in the substrate. The concentration of the non-dopant is in the range of about 6.times.10.sup.16 atoms/cm.sup.3 to about 3.times.10.sup.21 atoms/cm.sup.3. The substrate is then annealed at a temperature in the range of about 700.degree. C. to about 950.degree. C. to obtain the desired dopant profile.

Abstract: In accordance with the invention, a uniformly spaced three-dimensional array of quantum dots is fabricated by forming a uniform grid of intersecting dislocation lines, nucleating a regular two-dimensional array of quantum dots on the intersections, and replicating the array on successively grown layers. The substrate is partitioned into a grid of in-plane lattice parameters, thereby providing a regular array of preferential nucleation sites for the influx atoms of a different size during the epitaxial process. The regularity of the array results in an equal partition of the incoming atoms which, in turn, leads to uniformly sized islands nucleating on these preferred sites. The result is a uniformly sized, regularly distributed two-dimensional array of quantum dots which can be replicated in succeeding layers.

Abstract: A device with at least one noise-sensitive element, at least one noise-generating element, and a porous silicon barrier in the substrate is disclosed. The porous silicon barrier isolates the noise-sensitive element from the signals coupled into the substrate by the noise-generating element. A process for making this device is also disclosed.