Abstract: A display device includes a display panel, first and second conductive pads, a conductive adhesive layer and a circuit board. First and second leads are on a first substrate of the display panel and extended to be exposed at a side. A patterned electrode layer is on a second substrate of the display panel and partially exposed at the side. A spacer layer is on the first substrate and covers the first and second leads. A thickness of the spacer layer on the first lead is smaller than a thickness of the remaining part of the spacer layer. The first and second conductive pads are at the side of the display panel. The first conductive pads are extended to a space between the patterned electrode layer and the spacer layer on the first leads. The second conductive pads are connected to the second leads and the spacer layer thereon.

Abstract: An image displacement device includes a projection lens and a first grating. The projection lens has a lens group, and the lens group includes a first lens and a second lens, where no lens with refractive power is disposed between the first lens and the second lens. The first grating is switchable between a diffracting state and a non-diffracting state, and the first grating is disposed on one side of the first lens facing away from the second lens. A distance between the first grating and an aperture stop of the projection lens measured along an optical axis of the projection lens is smaller than a distance between the first grating and the second lens measured along the optical axis of the projection lens.

Abstract: A display panel including sub pixels, a plurality of first and second scan lines, a plurality of first and second data lines, a plurality of first and second auxiliary lines and first conductive vias is provided. The sub pixels are arranged into first rows arranged in a first direction and second rows arranged in a second direction. The second rows are electrically connected to the first and second scan lines in alternation and are electrically connected to the first and second data lines in alternation. Each first auxiliary line includes a first portion electrically connected to a corresponding first scan line and a second portion spaced away from the first portion. The second auxiliary lines are respectively located between two adjacent first rows. Each second scan line is electrically connected to a corresponding first scan line through at least one second auxiliary line.

Abstract: An electronic device including a substrate, transversal signal lines, a first vertical signal line, a second vertical signal line, and a first shielding vertical line is provided. The transversal signal lines, the first vertical signal line, the second vertical signal line, and the first shielding vertical line are disposed on the substrate. The first vertical signal line and the second vertical signal line are intersected with the transversal signal lines. The second vertical signal line is connected to one of the transversal signal lines. An orthogonal projection of the first shielding vertical line on the substrate is between an orthogonal projection of the first vertical signal line on the substrate and an orthogonal projection of the second vertical signal line on the substrate.

Abstract: A pixel array substrate including a substrate, data lines, gate lines, pixels, and transfer lines is provided. The data lines are disposed on the substrate and arranged in a first direction. The gate lines are disposed on the substrate and arranged in a second direction interlaced with the first direction. The pixels are disposed on the substrate, each of which includes an active device electrically connected to one of the data lines and one of the gate lines and a pixel electrode electrically connected to the active device. The transfer lines are arranged in the first direction and electrically connected to the gate lines, respectively. The pixels include first pixels. In a top view of the pixel array substrate, at least one of the pixel electrodes of the first pixels is partially overlapped with one of the transfer lines. A driving method of a pixel array substrate is also provided.

Abstract: A pixel array substrate, including scanning line pads, data line pads, scanning lines, data lines, gate transmission lines, pixels, a data line signal chip, and a scanning line signal chip, is provided. The scanning lines extend along a first direction. The data lines and the gate transmission lines extend along a second direction. The data lines are electrically connected to the data line pads. The scanning lines are electrically connected to the scanning line pads through the gate transmission lines. A ratio of a number of rows of pixels arranged in the first direction to a number of rows of pixels arranged in the second direction is X:Y. Each pixel includes m sub-pixels.

Abstract: One embodiment of the invention provides a pattern generation device includes a light source, a first HPDLC cell, and a second HPDLC cell. The first HPDLC cell is disposed downstream of a light path of the light source and contains a first phase modulation pattern. The second HPDLC cell is disposed downstream of the light path of the first HPDLC cell and contains a diffraction grating pattern.

Abstract: A display device includes a display panel, first and second conductive pads, a conductive adhesive layer and a circuit board. First and second leads are on a first substrate of the display panel and extended to be exposed at a side. A patterned electrode layer is on a second substrate of the display panel and partially exposed at the side. A spacer layer is on the first substrate and covers the first and second leads. A thickness of the spacer layer on the first lead is smaller than a thickness of the remaining part of the spacer layer. The first and second conductive pads are at the side of the display panel. The first conductive pads are extended to a space between the patterned electrode layer and the spacer layer on the first leads. The second conductive pads are connected to the second leads and the spacer layer thereon.

Abstract: A display panel includes a first substrate, pixel structures, a first common pad, a second substrate, a second common electrode, a display medium and a conductive particle. The pixel structures are disposed on an active area of the first substrate. The first common pad is disposed on a peripheral area of the first substrate, and is electrically connected to first common electrodes of the pixel structures. The second common electrode is disposed on the second substrate. The conductive particle is disposed on the first common pad, and is electrically connected to the first common pad and the second common electrode. The conductive particle includes a core and a conductive film disposed on a surface of the core, where the conductive film has a main portion and raised portions, and a film thickness of each of the raised portions is greater than a film thickness of the main portion.

Abstract: A pixel array substrate, including scanning line pads, data line pads, scanning lines, data lines, gate transmission lines, pixels, a data line signal chip, and a scanning line signal chip, is provided. The scanning lines extend along a first direction. The data lines and the gate transmission lines extend along a second direction. The data lines are electrically connected to the data line pads. The scanning lines are electrically connected to the scanning line pads through the gate transmission lines. A ratio of a number of rows of pixels arranged in the first direction to a number of rows of pixels arranged in the second direction is X:Y. Each pixel includes m sub-pixels.

Abstract: A pixel array substrate including a substrate, data lines, gate lines, pixels, and transfer lines is provided. The data lines are disposed on the substrate and arranged in a first direction. The gate lines are disposed on the substrate and arranged in a second direction interlaced with the first direction. The pixels are disposed on the substrate, each of which includes an active device electrically connected to one of the data lines and one of the gate lines and a pixel electrode electrically connected to the active device. The transfer lines are arranged in the first direction and electrically connected to the gate lines, respectively. The pixels include first pixels. In a top view of the pixel array substrate, at least one of the pixel electrodes of the first pixels is partially overlapped with one of the transfer lines. A driving method of a pixel array substrate is also provided.

Abstract: A pixel array substrate including a substrate, pixel structures, and transfer lines is provided. The pixel structures are disposed on the substrate. Each pixel structure includes a data line, a gate line, an active device, and a pixel electrode. The active device is electrically connected to the data line and the gate line. The pixel electrode is electrically connected to the active device. The pixel electrode defines alignment domains. The alignment domains have different alignment directions. The transfer lines are arranged in a first direction. Gate lines of the pixel structures are arranged in a second direction. The first direction and the second direction are interlaced. The transfer lines are electrically connected to the gate lines. The pixel structures include a first pixel structure. The transfer lines include a first transfer line. The first transfer line overlaps a boundary between the alignment domains of the first pixel structure.

Abstract: A display device includes a plurality of pixel structures, a plurality of first connection conductive wires and a plurality of second connection conductive wires. Each of the pixel structures includes a plurality of sub-pixels structures respectively corresponding to a plurality of display wavelengths. The sub-pixels structures are respectively coupled to a plurality of first data lines and second data lines. Each of the first connection conductive wires connects two of the first data lines coupled to two of the sub-pixels corresponding to same display wavelength. Each of the second connection conductive wires connects two of the second data lines coupled to two of the sub-pixels corresponding to same display wavelength.

Abstract: A pixel array substrate including a substrate, data lines, gate lines, pixels, and transfer lines is provided. The data lines are disposed on the substrate and arranged in a first direction. The gate lines are disposed on the substrate and arranged in a second direction interlaced with the first direction. The pixels are disposed on the substrate, each of which includes an active device electrically connected to one of the data lines and one of the gate lines and a pixel electrode electrically connected to the active device. The transfer lines are arranged in the first direction and electrically connected to the gate lines, respectively. The pixels include first pixels. In a top view of the pixel array substrate, at least one of the pixel electrodes of the first pixels is partially overlapped with one of the transfer lines. A driving method of a pixel array substrate is also provided.

Abstract: A pixel array substrate including a substrate, data lines, gate lines, pixels, and transfer lines is provided. The data lines are disposed on the substrate and arranged in a first direction. The gate lines are disposed on the substrate and arranged in a second direction interlaced with the first direction. The pixels are disposed on the substrate, each of which includes an active device electrically connected to one of the data lines and one of the gate lines and a pixel electrode electrically connected to the active device. The transfer lines are arranged in the first direction and electrically connected to the gate lines, respectively. The pixels include first pixels. In a top view of the pixel array substrate, at least one of the pixel electrodes of the first pixels is partially overlapped with one of the transfer lines. A driving method of a pixel array substrate is also provided.

Abstract: A display device includes a plurality of pixel structures, a plurality of first connection conductive wires and a plurality of second connection conductive wires. Each of the pixel structures includes a plurality of sub-pixels structures respectively corresponding to a plurality of display wavelengths. The sub-pixels structures are respectively coupled to a plurality of first data lines and second data lines. Each of the first connection conductive wires connects two of the first data lines coupled to two of the sub-pixels corresponding to same display wavelength. Each of the second connection conductive wires connects two of the second data lines coupled to two of the sub-pixels corresponding to same display wavelength.

Abstract: A pixel array substrate includes data lines, first gate lines, pixel structures, first common lines, and conductive line sets. The conductive line sets are arranged in a first direction. Each of the conductive line sets includes first conductive line groups and a second conductive line group sequentially arranged in the first direction. Each of the first conductive line groups includes second gate lines and a second common line. The second conductive line group includes first auxiliary lines and a second common line. An arrangement order of the second gate lines and the second common line of each of the first conductive line groups in the first direction are the same as an arrangement order of the first auxiliary lines and the second common line of the second conductive line group in the first direction, respectively.

Abstract: A pixel array substrate including a substrate, pixel structures, and transfer lines is provided. The pixel structures are disposed on the substrate. Each pixel structure includes a data line, a gate line, an active device, and a pixel electrode. The active device is electrically connected to the data line and the gate line. The pixel electrode is electrically connected to the active device. The pixel electrode defines alignment domains. The alignment domains have different alignment directions. The transfer lines are arranged in a first direction. Gate lines of the pixel structures are arranged in a second direction. The first direction and the second direction are interlaced. The transfer lines are electrically connected to the gate lines. The pixel structures include a first pixel structure. The transfer lines include a first transfer line. The first transfer line overlaps a boundary between the alignment domains of the first pixel structure.

Abstract: A display panel includes pixels and a first conductive element. Each pixel includes a first signal line, a second signal line, a third signal line, a first switch, a second switch, a third switch, a first pixel electrode, a second pixel electrode, a first capacitor, a second capacitor, a third capacitor, and an insulating layer. The first signal lines are arranged in a first direction. Orthogonal projections of a first electrode of a second capacitor of a first pixel, a first electrode of a third capacitor of the first pixel, and a first contact window of an insulating layer of the first pixel on a first substrate are arranged in the first direction. The first conductive element is electrically connected to a second electrode of the third capacitor of the first pixel and a second electrode of the second capacitor of the first pixel through the first contact window.

Abstract: A pixel structure includes a scan line, a data line, a reference voltage line, a first transistor, a second transistor, a third transistor, a first pixel electrode and a second pixel electrode. The reference voltage line is separated from the data line and intersected with the scan line. A first electrode of the second transistor, a second electrode of the second transistor and a first electrode of the third transistor have straight line portions overlapped with a second semiconductor pattern of the second transistor and a third semiconductor pattern of the third transistor. Both ends of each of the straight line portions are located outside a normal projection region of a first semiconductor pattern of the first transistor, a normal projection region of the second semiconductor pattern of the second transistor and a normal projection region of the third semiconductor pattern of the third transistor.