Abstract: A signal transmission line check method to be executed by a computing device is described. A to-be-checked signal transmission line group in a displayed printed circuit board (PCB) layout is determined. Whether all signal transmission lines of the to-be-checked signal transmission line group are laid out in a same layer of the displayed PCB layout is checked according to an input serial number of a chipset and layer properties of the to-be-checked signal transmission lines. The signal transmission lines that do not satisfy design standards are determined when not all of the to-be-checked signal transmission lines are laid out in a same layer. A related computing device is also disclosed.

Abstract: In a method for checking a wiring diagram in a printed circuit board (PCB) design, a pair of differential signal lines in a PCB file is located according to a designation of a user. Components connected by the differential signal lines and vias which the differential signal lines pass through are obtained from the PCB file. A determination of whether obtained components and the obtained vias meet predetermined requirements is made by checking whether copper foils between each pair of the obtained vias or between pins of the obtained components in ground layers and power layers of the PCB file are hollowed.

Abstract: A signal transmission line check method to be executed by a computing device is described. A to-be-checked signal transmission line group in a displayed printed circuit board (PCB) layout is determined. Whether all signal transmission lines of the to-be-checked signal transmission line group are laid out in a same layer of the displayed PCB layout is checked according to an input serial number of a chipset and layer properties of the to-be-checked signal transmission lines. The signal transmission lines that do not satisfy design standards are determined when not all of the to-be-checked signal transmission lines are laid out in a same layer. A related computing device is also disclosed.

Abstract: In a method for checking wiring diagrams, one element is selected from a first printed circuit board (PCB) file. An element corresponding to the selected element in a second PCB file is searched according to information of the selected element, then the information is recorded into a different element list of the first PCB file, when the second PCB file does not have a corresponding element. The information is recorded into a same element list, when the second PCB file has a corresponding element and the corresponding element has the same information with the element in the first PCB file. The second PCB file and the same element list are compared to locate elements which are included in the second PCB file but not included in the same element list, and the information of the located elements is recorded into a different element list of the second PCB file.

Abstract: In a method for checking the length of a signal trace between a coupling capacitor and a via in a printed circuit board (PCB) design using a computing device, a PCB file is obtained from a storage device to simulate a PCB design. The signal trace between the coupling capacitor and the via is filtered on the PCB design, and a real length of the signal trace between the coupling capacitor and the via is calculated. If the real length is greater than a specified length, the method locates a position of the via on the PCB design and generates a design report indicating that the signal trace between the coupling capacitor and the via is unqualified. The method further displays information of the signal trace on a display device of the computing device.

Abstract: A device and a method reads a circuit printed circuit (PCB) layout file, extracts arrangement information of all the interference source components and signal transmission lines of the PCB layout file, and selects a interference source component from the PCB layout file, then determines if there is any signal transmission line is laid under the selected interference source component.

Abstract: A computer-based method and a computing device for checking differential pairs of a printed circuit board layout are provided. The computing device determines the via pitch between switching vias of a differential pair according to the coordinates of the centers of the switching vias, determines the via gap between the switching vias of adjacent two differential pairs according to the radius and the coordinates of the centers of the switching vias, and determines that the switching vias does not satisfy design standards if the via pitch does not fall in an input via pitch range, or the via gap does not fall in an input via gap range.

Abstract: In a computing device, computerized method, and a non-transitory storage medium, plug-in capacitors are selected from capacitors in a wiring diagram according pin information of the capacitors. A straight line is constructed for each of the plug-in capacitors according to size of holes where pins of the plug-in capacitor are to be inserted into. Paths of all transmission lines in the wiring diagram are obtained, and a determination of, whether any of the paths has at least one intersection point with at least one constructed straight line, is made. One or more paths, which have at least one intersection point with at least one constructed straight line, are recorded into a path list. The path list is then outputted using the computing device.

Abstract: In a method for checking layout of a printed circuit board (PCB) using an electronic device, a signal line is selected from a layout diagram of the PCB. The method searches for signal lines which have an acute angle when deviating from a straight line in the layout diagram of the PCB. The method further locates attribute data of the searched signal lines in the layout diagram of the PCB, and displays the attribute data of the searched signal lines on a display device of the electronic device.

Abstract: A computer-based method and a computing device for checking signal transmission lines of a printed circuit board (PCB) layout are provided. The computing device identifies differential pairs in a currently run PCB layout according to an information file for the currently run PCB layout, checks whether any signal transmission line is routed between switching vias of each differential pair according to the information file for the currently run PCB layout, and displays a routing error window to display information of each misrouted signal transmission line.

Abstract: A computing device and a method reads design standards of signal transmission lines in a printed circuit board (PCB) layout file, and determines a minimum reference length of line segments of the signal transmission lines from the design standards. The device and method then selects a signal transmission line from a circuit board, and computes an actual length of each line segment of the selected signal transmission line. If each actual length is more than or equal to the minimum reference length, the device and method determines length design of the selected signal transmission line satisfies the design standards. Otherwise, if any actual length is less than the minimum reference length, the device and method determines the length design of the signal transmission line does not satisfy the design standards.

Abstract: In a method for checking layout of a printed circuit board (PCB) using an electronic device, a signal line is selected from a layout diagram of the PCB. The method searches for signal lines which have an acute angle when deviating from a straight line in the layout diagram of the PCB. The method further locates attribute data of the searched signal lines in the layout diagram of the PCB, and displays the attribute data of the searched signal lines on a display device of the electronic device.

Abstract: An electronic device and a method for checking layout distance of a printed circuit board (PCB) including presetting a checking condition to determine a reference layer. A high speed signal path is selected from a PCB design file, and a layer where the selected high speed signal path is located can be determined A reference layer of the determined layer is determined according to the checking condition, and a split line of the reference layer is determined. A shortest distance between each segment of the selected high speed signal path and the split line is calculated. If the shortest distance between a segment and the split line is less than the standard distance, layout of the segment is determined to be invalid.

Abstract: A method for die attaching is disclosed. At first, at least one die and a die-attach preform are separately provided. The die-attach preform is picked and placed upon a die carrier. Then, the die is picked and placed upon the die-attach preform. The die and the die carrier are heated and clipped, so that the die-attach preform can adhere the die and the die carrier at the same time.

Abstract: A rotational facility includes a barrel coupled to a driving device for being rotated and driven by the driving device, a wheel rotatably attached onto the barrel, and a braking device secured to the wheel for engaging with the barrel and for braking the wheel relative to the barrel. The braking device includes a housing secured to the wheel and one or more actuating members received in the housing for engaging with the barrel to brake the housing and the wheel relative to the barrel. The housing includes a brake member for engaging with and for actuating the actuating member to engage with the barrel. The housing includes a peripheral channel formed by inner and outer peripheral walls to receive the brake member.

Abstract: A pad layout of a printed circuit board includes a first and a second pad symmetrically arranged on the PCB for cooperatively receiving either a first surface mounted component (SMC) or a second surface mounted component (SMC). Each of the SMCs includes a first footprint and a second footprint. The first pad has a polygonal shape corresponding to a minimum sized shape that accommodates both a shape of the first footprint of the first SMC and a shape of the first footprint of the second SMC. The second pad has a polygonal shape corresponding to a minimum sized shape that accommodates both a shape of the second footprint of the first SMC and a shape of the second footprint of the second SMC.

Abstract: A layout structure of ball grid array is provided. The layout structure includes: a substrate having a margin area; a plurality of solder ball pads laid on the substrate; a plurality of interconnection vias each electrically coupled to a corresponding one of the plurality of solder ball pads; and at least one of the plurality of interconnection vias arrayed on the margin area so that no interconnection vias are arrayed between one of the plurality of interconnection vias and an edge of the margin area.

Abstract: A printed circuit board includes a reference layer, a through hole defined in the reference layer, and a plurality of insulating areas are defined in the reference layer around the through hole. The copper around the through hole is separated by the insulating areas and forms a plurality of copper strips. The metal surface area around the through hole available for heat dissipation is reduced to slow down heat distribution. Defect formation is thus reduced when the PCB is in a reflow process.

Abstract: A pad is adapted for selectively receiving a first surface mounted component (SMC) and a second SMC on a printed circuit board. The first SMC and the second SMC include a number of footprints respectively. The pad includes a first portion for receiving the first SMC, a second portion for receiving the second SMC. Configurations and sizes of the first portion and the second portion are same with the ones of the footprints of the first SMC and the second SMC respectively. The second portion is overlapped with the first portion. The pad can selectively receive one of the first SMC and the second SMC.

Abstract: A pad layout of a printed circuit board includes a first and a second pad symmetrically arranged on the PCB for cooperatively receiving either a first surface mounted component (SMC) or a second surface mounted component (SMC). Each of the SMCs includes a first footprint and a second footprint. The first pad has a polygonal shape corresponding to a minimum sized shape that accommodates both a shape of the first footprint of the first SMC and a shape of the first footprint of the second SMC. The second pad has a polygonal shape corresponding to a minimum sized shape that accommodates both a shape of the second footprint of the first SMC and a shape of the second footprint of the second SMC.