Patents by Inventor Ya-Ling Huang

Ya-Ling Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060121644
    Abstract: A method for die attaching is disclosed. At first, at least one die and a die-attach preform are separately provided. The die-attach preform is picked and placed upon a die carrier. Then, the die is picked and placed upon the die-attach preform. The die and the die carrier are heated and clipped, so that the die-attach preform can adhere the die and the die carrier at the same time.
    Type: Application
    Filed: December 5, 2005
    Publication date: June 8, 2006
    Inventors: Hung-Ta Hsu, Tzu-Bin Lin, Ya-Ling Huang, Ya-Yu Hsieh
  • Publication number: 20060102700
    Abstract: A printed circuit board (100) includes a plurality of through-holes (26) defined therein, and a plurality of solder pads (20) defined to surround the through holes (26) respectively. Each of the solder pads (20) includes a first soldering zone (22) for accommodating solder used in a soldering process and a second soldering zone (28) in communication with the first soldering zone (22) for receiving excess solder extravasating from the first soldering zone (22). An axis of each of the solder pads (22) and a direction opposite to a movement direction of the printed circuit board (100) in the soldering process defines a predetermined angle.
    Type: Application
    Filed: December 29, 2004
    Publication date: May 18, 2006
    Applicant: HON HAI Precision Industry CO., LTD.
    Inventors: Ya-ling Huang, Di Li, Yu-cui He
  • Patent number: 7005749
    Abstract: A flip chip package structure includes a substrate, a chip, solder bumps, a heat sink, a thermal interface material (TIM), and solder balls. The substrate has an upper surface and a lower surface and further has a receiving area. The receiving area has a bottom in the substrate and an opening formed on the upper surface. Several solder bumps are disposed in the receiving area. The chip is disposed on the upper surface of the substrate, and covers the opening. The front surface of the chip is electrically coupled to the bottom via the solder bumps. The heat sink is attached to the upper surface of the substrate and the back surface of the chip through the adhesion of TIM. Several solder balls are disposed on the lower surface of the substrate.
    Type: Grant
    Filed: July 27, 2004
    Date of Patent: February 28, 2006
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Hung-Ta Hsu, Tzu-Bin Lin, Ya-Ling Huang
  • Publication number: 20050140005
    Abstract: A chip package structure is disclosed. The chip package structure includes an inner molding compound with a low modulus covering the chip and an outer molding compound covering the inner molding compound. The outer molding compound has a modulus larger than then modulus of the inner molding compound.
    Type: Application
    Filed: December 29, 2004
    Publication date: June 30, 2005
    Inventors: Ya-Ling Huang, Tzu-Bin Lin, Hung-Ta Hsu
  • Publication number: 20050139974
    Abstract: A chip package structure is disclosed. The chip package structure includes an inner molding compound with a low modulus and a heat sink covering the chip. An outer molding compound having a modulus larger than the modulus of the inner molding compound can be applied around the heat sink.
    Type: Application
    Filed: December 29, 2004
    Publication date: June 30, 2005
    Inventors: Ya-Ling Huang, Hung-Ta Hsu, Tzu-Bin Lin
  • Publication number: 20050139994
    Abstract: A semiconductor package includes a die attached to a substrate. Multitudes of conductive structures are conductively connected the die and the substrate. One molding compound encapsulates the die, and thermal interface material is on the molding compound. Next, a heat sink is on the thermal interface material. The mold compound material performs a coefficient of thermal expansion smaller than the heat sink so as to prevent the die or substrate from the damages of internal stresses.
    Type: Application
    Filed: December 29, 2004
    Publication date: June 30, 2005
    Inventors: Hung-Ta Hsu, Tzu-Bin Lin, Ya-Ling Huang
  • Publication number: 20050029672
    Abstract: A flip chip package structure includes a substrate, a chip, solder bumps, a heat sink, a thermal interface material (TIM), and solder balls. The substrate has an upper surface and a lower surface and further has a receiving area. The receiving area has a bottom in the substrate and an opening formed on the upper surface. Several solder bumps are disposed in the receiving area. The chip is disposed on the upper surface of the substrate, and covers the opening. The front surface of the chip is electrically coupled to the bottom via the solder bumps. The heat sink is attached to the upper surface of the substrate and the back surface of the chip through the adhesion of TIM. Several solder balls are disposed on the lower surface of the substrate.
    Type: Application
    Filed: July 27, 2004
    Publication date: February 10, 2005
    Inventors: Hung-Ta Hsu, Tzu-Bin Lin, Ya-Ling Huang