Abstract: Implementations of the present application provide a semiconductor device, a fabrication method and a memory system. The semiconductor device includes a plurality of semiconductor pillars arranged in an array and a word line structure. The plurality of semiconductor pillars extend along a first direction and include at least one side face, wherein the plurality of semiconductor pillars are arranged in rows along a second direction perpendicular to the first direction. The word line structure is located between a first row and a second row of semiconductor pillars that are adjacent, and includes a first word line structure and a second word line structure spaced apart from the first word line structure, wherein the first word line structure is connected with a side face of the first row of semiconductor pillars, and the second word line structure is connected with a side face of the second row of semiconductor pillars.

Abstract: The invention relates to a field of polymer preparation and discloses a method for promoting phase-separation of polymer solution. The phase-separation method of polymer solution of the invention comprises: at least a portion of the polymer solution is subjected to a heat treatment under flowing so that the polymer solution is divided into a clear liquid phase and a concentrated liquid phase, wherein the Reynolds number of the polymer solution flowing is 0.2-30. By performing the heat treatment under specific Reynolds number conditions, the invention permits to reduce the temperature of phase-separation of solution, reduce the time of phase-separation of solution, and significantly reduce the material consumption and energy consumption of the entire process, compared with the existing technology that only performs phase-separation through heat treatment.

Abstract: A memory system comprises: a memory device including a first word line; and a memory controller coupled to the memory device and configured to: acquire the number of read failure bits of a memory cell page coupled to the first word line; determine whether the number of read failure bits of the memory cell page is greater than a preset threshold; and control the memory device to perform a reprogram operation on the memory cell page in response to the number of read failure bits of the memory cell page being greater than the preset threshold.

Abstract: A passive infrared (PIR) sensor system, includes a PIR sensor configured to produce an output signal in response to receiving infrared (IR) radiation, an electronic shutter positionable in a field of view (FOV) of the PIR sensor, wherein the electronic shutter includes a liquid crystal (LC) material, wherein the electronic shutter includes a first state providing a first transmissivity of IR radiation through the electronic shutter and a second state providing a second transmissivity of IR radiation through the electronic shutter that is less than the first transmissivity, and a shutter actuator configured to apply an actuation signal to the electronic shutter to actuate the electronic shutter between the first state and the second state.

Abstract: In some examples, a peripheral circuit is configured to: when performing a first read operation on memory cells coupled to a selected word line, apply a first pass voltage to a first word line, apply a second pass voltage to a second word line, and apply a third pass voltage to a third word line, wherein the first word line comprises at least one word line physically located above and below the selected word line respectively, both the second word line and the third word line comprise word lines physically located on a side of the first word line away from the selected word line, memory cells coupled to the second word line comprise programmed memory cells, memory cells coupled to the third word line comprise unprogrammed memory cells, and the first pass voltage, the second pass voltage and the third pass voltage are all different.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip floorplan. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip floorplan, comprising placing a respective node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the node to be placed at the time step to a position from the plurality of positions using the score distribution.

Abstract: A passive infrared (PIR) sensor system, includes a PIR sensor configured to produce an output signal in response to receiving infrared (IR) radiation, an electronic shutter positionable in a field of view (FOV) of the PIR sensor, wherein the electronic shutter includes a liquid crystal (LC) material, wherein the electronic shutter includes a first state providing a first transmissivity of IR radiation through the electronic shutter and a second state providing a second transmissivity of IR radiation through the electronic shutter that is less than the first transmissivity, and a shutter actuator configured to apply an actuation signal to the electronic shutter to actuate the electronic shutter between the first state and the second state.

Abstract: The present application discloses a patterning method, a semiconductor structure and a memory. The patterning method includes: after forming a mandrel structure in a mask layer on a side of a to-be-etched layer, removing part of the mandrel structure to form a first trench with a smaller length and a second trench with a larger length, and forming a first mask pattern and a second mask pattern through the first trench and the second trench so as to form a first patterned structure and a second patterned structure of different lengths. The present application can improve the applicability of the patterning method, and reduce the process difficulty and cost of fine patterning for forming patterns of different sizes, such that the patterning method provided by the present application can meet more process requirements.

Abstract: The present application discloses a semiconductor device and a fabrication method thereof, and a memory system. The device includes a plurality of semiconductor pillars extending in a third direction, and a plurality of gate structures and shielding structures extending along a first direction. The gate structures and the shielding structures are in a staggered distribution along a second direction, and the semiconductor pillars are located between the shielding structures and the gate structures that are adjacent. Sizes of the gate structures along the first direction are smaller than sizes of the shielding structures along the first direction, and orthographic projections of the gate structures are within ranges of orthographic projections of the shielding structures along the second direction.

Abstract: Implementations of the present application disclose a semiconductor device, a fabrication method of a semiconductor device and a memory system. The semiconductor device includes a plurality of word line groups and separating structures disposed between two adjacent word line groups. The word line groups and the separating structures extend in the first lateral direction. In the first lateral direction, the length of a word line group is greater than the length of a separating structure; wherein a word line group includes two word lines and two partition structures. In a same word line group, the word lines and the partition structures are disposed as a closed loop. In the second lateral direction perpendicular to the first lateral direction, there are overlaps between partition structures and separating structures.

Abstract: Examples include forming first trenches extending along a first direction on a first side of a semiconductor layer, and forming an insulation layer within the first trenches; forming second trenches extending along a second direction on the first side, the depths of the second trenches less than depths of the first trenches, the first and second directions intersecting; forming a first gate insulation layer and first gate conductive layer sequentially on inner walls of the second trenches; removing part of the semiconductor layer, part of the insulation layer and part of the first gate insulation layer from a second side of the semiconductor layer facing away from the first side, to expose the first gate conductive layer; and removing a part of the first gate conductive layer from the second side, to divide the first gate conductive layer into first gates located on opposite sidewalls of the second trenches respectively.

Abstract: A semiconductor structure and a method for preparing the same are provided. The semiconductor structure includes: a substrate having a plurality of active regions that are arrayed. Each of the plurality of active regions includes an active portion and an active extension portion. A word line gate structure is positioned in the substrate. The word line gate structure runs through the plurality of active regions. The word line gate structure includes a word line layer and a word line isolation layer. The active extension portion covers a surface of the active portion and is at least partially positioned on the word line gate structure. A word line isolation extension portion is positioned in the active extension portion, where the word line isolation extension portion is connected to the word line isolation layer and formed on a surface of the word line isolation layer.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip floorplan. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip floorplan, comprising placing a respective node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the node to be placed at the time step to a position from the plurality of positions using the score distribution.

Abstract: This document describes techniques and systems that enable a range extender device. The techniques and systems include a user device that includes a housing with an audio sensor, a heat sink assembly, a circuit board assembly, and a speaker assembly positioned within the housing. The housing includes a top housing member connected to a bottom housing member. The top housing member includes a concave-down top-end portion connected to a generally-cylindrical vertical wall via rounded corners. The heat sink assembly includes a heat sink and one or more antennas positioned proximate to an inner surface of the vertical wall. The circuit board assembly is positioned within the housing and proximate to the heat sink assembly, and the speaker assembly is positioned within the housing and connected to the circuit board assembly. Also, a light ring assembly is connected to a bottom exterior surface of the bottom housing member.

Abstract: In an embodiment, the present disclosure pertains to a nanocarrier having a shell and a core disposed within the shell. In some embodiments, the shell includes a functionalized surface. In an additional embodiment, the present disclosure pertains to a method of drug delivery. In general, the method includes administering a nanocarrier to a subject, targeting, by the nanocarrier, an area in the subject, and releasing a composition having the drug to the area. In some embodiments, the nanocarrier has a shell and a core disposed within the shell. In some embodiments, the shell includes a functionalized surface.

Abstract: A semiconductor structure and method for manufacturing thereof are provided. The semiconductor structure includes a vertical transistor. The vertical transistor includes a semiconductor body extending in a first direction. The semiconductor body includes a source/drain at one end of the semiconductor body. The vertical transistor also includes a gate structure coupled to at least one side of the semiconductor body. The gate structure includes a gate dielectric and a gate electrode. The vertical transistor further includes a silicide. At least part of the silicide is above the source/drain. An area of the silicide is larger than an area of a first surface of the source/drain. The first surface is vertical to the first direction.

Abstract: A method includes providing a tapered roller bearing including an outer ring having a raceway surface, an inner ring having a raceway surface and a plurality of tapered rollers each having a rolling surface and a large end-face; optimizing a surface roughness of at least one surface selected from the following set of surfaces: the outer ring raceway surface, the inner ring raceway surface, the rolling surfaces of the tapered rollers and the large end faces of the tapered rollers; and black oxidizing the at least one first surface.

Abstract: A bearing cage for holding rollers between an outer ring and an inner ring of a bearing includes a first side ring, a second side ring axially spaced from the first side ring and a plurality of circumferentially spaced bridges connecting the first side ring and the second side ring. The first side ring includes at least one radially inward extending circumferential projection, and the at least one projection may be a plurality of projections separated by a plurality of gaps.

Abstract: A foam pad structure having a protective film includes a substrate layer, a hot glue layer, a printed pattern layer, and an adhesive film. The substrate layer is made of a foam material. The substrate layer has two surfaces arranged oppositely on its upper and lower sides. The hot glue layer is coated on at least one of the two surfaces of the substrate layer. The hot glue layer has an adhesive surface facing away from the substrate layer. The printed pattern layer is composed of a pigment containing the same composition as the hot glue layer. The printed pattern layer is printed on the adhesive surface of the hot glue layer. The hot glue layer and the printed pattern layer are melted between the substrate layer and the adhesive film.

Abstract: The present disclosure provides a fixed-position defect doping method for a micro-nanostructure based on a self-alignment process, including: S1, sequentially forming a sacrificial layer and a photoresist layer on a surface of a crystal substrate; S2, performing a lithography on the photoresist layer to form a mask hole according to a micro-nano pattern; S3, performing an isotropic etching on the sacrificial layer through the mask hole, and amplifying the micro-nano pattern to the sacrificial layer; S4, performing an ion implantation doping on an exposed crystal surface below the mask hole; S5, removing the photoresist layer, and depositing a mask material; S6, removing the sacrificial layer, and transferring a micro-nano amplified pattern in the sacrificial layer to a mask material pattern; and S7, etching an exposed crystal surface, and removing the mask material on the surface and forming a specific defect by annealing.