Abstract: A manufacturing method of a color filter including following steps is provided. First, a partition is formed on a substrate to form a plurality of pixel regions on the substrate. Next, a color pigment is provided along a continuous pigment-providing route, so as to form the color pigment on a sequence of pixel regions among the plurality of pixel regions and the partition. The method mentioned above can prevent the unfilled phenomenon of the pigment around the corners of the pixel region. Besides, a liquid crystal display panel having the color filter is also provided.

Abstract: Isolated nucleic acid comprising a nucleotide sequence that codes for a mutant mammalian Nav1 protein are disclosed.

Abstract: The present disclosure involves systems, products, and methods for automatically generating a CAPA plan. One method includes operations for identifying an issue associated with a business system; identifying a set of information associated with the issue including a plurality of evaluation factors defining the issue; identifying a set of weighting values associated with the issue, each weighting values associated with a particular evaluation factor; evaluating the issue based on the plurality of evaluation factors combined with the corresponding weighting value, determining at least one root cause for the issue based on the evaluation results, identifying at least one corrective or preventive action based at least in part on the at least one determined root cause for the issue, and automatically generating the CAPA plan including the at least one determined root cause and the at least one identified corrective or preventive action associated with the issue.

Abstract: A branched polymer represented by formula (I): wherein at least one of L1, L2, L3, and L4 is a univalent organic group represented by formula (II): wherein L5, L6 and L7 are independently hydrogen or a univalent organic group, D1, D2 and D3 being independently a single bond or a divalent group, at least one of D1, D2, and D3 containing in which R1 is hydrogen or a methyl group and n is an integer ranging from 1 to 1000; and the remainder of L1, L2, L3, and L4 being independently hydrogen or a univalent organic group represented by formula (III): wherein R is a univalent end group, with the proviso that, when one of the remainder is hydrogen, the others of the remainder cannot be hydrogen.

Abstract: A method for jetting color ink includes determining an initial voltage value of a nozzle, wherein the initial voltage value corresponds to a predetermined jetting volume of the nozzle; determining a maximum adjusting voltage value of the nozzle, wherein the maximum adjusting voltage value may correspond to an allowable error value of the predetermined jetting volume; combining the initial voltage value with an adjusting voltage value to obtain a jetting voltage, wherein the adjusting voltage value may be randomly selected between zero to the maximum adjusting voltage value; and jetting the color ink from the nozzle according to the jetting voltage onto a sub-pixel in a pixel.

Abstract: The present invention relates to a process for manufacturing a porous epoxy network, especially a porous epoxy membrane. The process according the present invention comprises the steps of: providing a reactant solution comprising an epoxy resin, a solvent and a curing agent; performing a first curing process to transform the reactant solution to a gel; and performing a second curing process to essentially remove the remaining solvent and transform the gel to form a porous epoxy network with open pores; wherein the curing agent is a tertiary amine.

Abstract: A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a source/drain region adjacent the gate dielectric; a silicide region on the source/drain region; a metal layer on top of, and physical contacting, the silicide region; an inter-layer dielectric (ILD) over the metal layer; and a contact opening in the ILD. The metal layer is exposed through the contact opening. The metal layer further extends under the ILD. The semiconductor structure further includes a contact in the contact opening.

Abstract: A method and apparatus involve providing a substrate having a dielectric layer formed thereon, forming a photoresist mask over the dielectric layer, the photoresist mask defining an opening, etching the dielectric layer through the at least one opening in the photoresist mask, treating a portion of the photoresist mask with an etching species, and removing the treated photoresist mask with a supercritical fluid. The etching, treating, and removing can be performed in one chamber.

Abstract: A method or screen for assessing the potential of a compound to treat a pathological condition, such as arrhythmia, which is manifested by an increased late sodium current in a heart is disclosed. The method employs a mutant sodium channel protein having an amino acid sequence in which one or more amino acids among the ten amino acids occurring at the carboxy end of the S6 segments of D1, D2, D3 or D4 domains of mammalian Nav1 differs from the amino acid in wild-type Nav1 by substitution with tryptophan, phenylalanine, tyrosine or cysteine. Cells transfected with a nucleic acid that encodes a mutant mammalian Nav1 protein, as well as isolated nucleic acid comprising a nucleotide sequence that codes for a mutant mammalian Nav1 protein are disclosed.

Abstract: A semiconductor device includes a channel region; a gate dielectric over the channel region; a gate electrode over the gate dielectric; and a first source/drain region adjacent the gate dielectric. The first source/drain region is of a first conductivity type. At least one of the channel region and the first source/drain region includes a superlattice structure. The semiconductor device further includes a second source/drain region on an opposite side of the channel region than the first source/drain region. The second source/drain region is of a second conductivity type opposite the first conductivity type. At most, one of the first source/drain region and the second source/drain region comprises an additional superlattice structure.

Abstract: A semiconductor device includes a channel region; a gate dielectric over the channel region; a gate electrode over the gate dielectric; and a first source/drain region adjacent the gate dielectric. The first source/drain region is of a first conductivity type. At least one of the channel region and the first source/drain region includes a superlattice structure. The semiconductor device further includes a second source/drain region on an opposite side of the channel region than the first source/drain region. The second source/drain region is of a second conductivity type opposite the first conductivity type. At most, one of the first source/drain region and the second source/drain region comprises an additional superlattice structure.

Abstract: A housing functioning as an antenna includes: a decorative film, an antenna member having a connecting pole, and a base body. The housing is formed by injection molding a molten plastic material over the decorative film, the base body is formed from the molten plastic material, and the antenna member is embedded between the decorative film and the base body, the connecting pole is exposed to the outside. A method for fabricating the housing is also described.

Abstract: A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a source/drain region adjacent the gate dielectric; a silicide region on the source/drain region; a metal layer on top of, and physical contacting, the silicide region; an inter-layer dielectric (ILD) over the metal layer; and a contact opening in the ILD. The metal layer is exposed through the contact opening. The metal layer further extends under the ILD. The semiconductor structure further includes a contact in the contact opening.

Abstract: A method or screen for assessing the potential of a compound to treat a pathological condition, such as arrhythmia, which is manifested by an increased late sodium current in a heart is disclosed. The method employs a mutant sodium channel protein having an amino acid sequence in which one or more amino acids among the ten amino acids occurring at the carboxy end of the S6 segments of D1, D2, D3 or D4 domains of mammalian Nav1 differs from the amino acid in wild-type Nav1 by substitution with tryptophan, phenylalanine, tyrosine or cysteine. Cells transfected with a nucleic acid that encodes a mutant mammalian Nav1 protein, as well as isolated nucleic acid comprising a nucleotide sequence that codes for a mutant mammalian Nav1 protein are disclosed.

Abstract: Methods of preparing a composition comprising non-ionic, radioactive gold nanoparticles (R-GNPs) are disclosed. The method comprises: a) providing a solution comprising gold (Au-197) ions; and b) exposing the solution to neutron irradiation to generate a composition comprising non-ionic R-GNPs. Alternatively, the method comprises: a) providing a solution that comprises a composition comprising gold (Au-197) nanoparticles (GNPs); and b) exposing the GNP solution to neutron irradiation to generate a composition comprising non-ionic R-GNPs. Compositions that comprises non-ionic R-GNPs encapsulated within and/or anchored to MSNs, and methods of making the same are also disclosed.

Abstract: The main goals of the invention are to develop the long-term release of Granisetron injection implant composition with biodegradable polymer and to develop relative processing. Granisetron is mixed with different biodegradable polymers, and then hot melt extrusion technique with different diameter, temperature, rate of extrusion and holding time is applied to make implant. In vitro dissolution of the Granisetron injection implant composition shows the component continued release of the drug for over 7 days.

Abstract: A microfluidics switch with moving planes has a first substrate with some holes and a second substrate with some micro-channels. Herein, the relative planes of both substrates are covered by a hydrophobic material. Therefore, while the substrates are neighboring and relatively moving, the overlap relation between the holes and the micro-channels are varied and a switch function is provided. Further, by using the hydrophobic material, while the distance between substrates is smaller than the height of drop of each liquid inputted into the holes, the fluids can not fluid between the planes and then different micro-channels are isolated from each other.

Abstract: A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a source/drain region adjacent the gate dielectric; a silicide region on the source/drain region; a metal layer on top of, and physical contacting, the silicide region; an inter-layer dielectric (ILD) over the metal layer; and a contact opening in the ILD. The metal layer is exposed through the contact opening. The metal layer further extends under the ILD. The semiconductor structure further includes a contact in the contact opening.

Abstract: A semiconductor device includes a channel region; a gate dielectric over the channel region; a gate electrode over the gate dielectric; and a first source/drain region adjacent the gate dielectric. The first source/drain region is of a first conductivity type. At least one of the channel region and the first source/drain region includes a superlattice structure. The semiconductor device further includes a second source/drain region on an opposite side of the channel region than the first source/drain region. The second source/drain region is of a second conductivity type opposite the first conductivity type. At most, one of the first source/drain region and the second source/drain region comprises an additional superlattice structure.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate, forming a dielectric layer over the semiconductor substrate, treating the dielectric layer with a carbon containing group, forming a conductive layer over the treated dielectric layer, and patterning and etching the dielectric layer and conductive layer to form a gate structure. The carbon containing group includes an OCH3 or CN species.