Abstract: A regulator circuit, embedded in a device, which is adapted to draw power from a power source internal to the device and a power source external to the device. The regulator circuit includes a first circuit segment for regulating power supplied by the internal power source, a second circuit segment for regulating power supplied by the external power source, an output circuit segment that monitors the output of the regulator circuit and supplies regulated power to the device. Additionally, responsive to the monitoring the regulator circuit preferentially draws power from the second circuit segment and complements the drawn power with power from the first circuit segment to maintain a regulated power supply at the output.

Abstract: The invention provides an apparatus and a method for generating spread spectrum clock signals, the method comprising the steps of: (1.a) determining a relationship R between a fundamental period T of a clock signal and a period offset DT; (1.b) receiving a clock signal having the fundamental period T; (1.c) of adjusting the delay step DS so that the spread spectrum clock signal to be produced during step (1.d) has a period that ranges between (T−DT) and (T+DT). (1.d) producing a spread spectrum clock signal having a period that ranges between (T−DT) and (T+DT). Steps (1.c) and (1.d) can be repeated either constantly, in manner that compensated for either variations in the delay step, in the variable delay period and/or for changes in the fundamental period.

Abstract: A phase lock loop having an bandwidth that does not depend upon N. The phase lock loop comprising: a controlled oscillator, a frequency divider by N, a phase detector for producing an error signal ER, and an adjustable converter, coupled to the phase detector and to the current controlled oscillator, for receiving ER and providing the controlled oscillator a control signal such that that the (Fico/N) ranges between a minimum value of Fmin and a maximal value of Fmax, wherein Fref=(Fmin+Fmax)/2.

Abstract: Apparatus and method of dynamic element matching overcomes problems associated with noise arising from mismatch errors thereby enabling high quality devices and systems to be made from cheaper, low tolerance components.

Abstract: An analog-to-digital converter (200) has a first stage (207) to integrate and quantize the difference between a feedback signal (R) and an input signal (X) to a first intermediate signal (Y1) with a first resolution (M1), a second stage (208) to integrate and quantize the first intermediate signal (Y1) to a second intermediate signal (Y2) with a second, lower resolution (M2), a feedback stage (260) to convert the second intermediate signal (Y2) to the feedback signal (R), and a third stage (206, 270, 280, 285) to differentiate the first intermediate signal (Y1) to a third intermediate signal (W1), to delay the second intermediate signal (Y2) to a fourth intermediate signal (W2), and to add the third and fourth intermediate signals (W1, W2) to an output signal (Y) having a resolution that results from the sum of the first (M1) and second (M2) resolutions.

Abstract: A low noise transconductance device having a transconduction comprising of two transconductive elements and a load, the transconduction of the first element equals N*Gm1, the transconduction of the second element equals Gm1/N, and a load having a resistance of 1/Gm1. The output of the first device is coupled to the input of the second element, and the load is coupled in parallel to the output of the first element. The accumulative transconduction of the device equals Gm1, and the noise generated by the device is lower than the noise generated by a single transconduction device having a gain of Gm1. N>2.

Abstract: A high-speed voltage shifter/amplifier, a sigma delta modulator having a high-speed voltage shifter/amplifier and method for performing an amplification/a voltage shift to an analog signal. The voltage shifter/amplifier comprising a capacitor and an isolator; the isolator is coupled to the capacitor. The capacitor is adapted to receive a control signal, to be charged by an input signal, and to provide an output signal. The capacitor has a capacitance that is responsive to a level of the control signal, and a change in the capacitance of the capacitor forces a change in a level of the output signal; and the isolator is adapted to electrically isolate the capacitor when the capacitance is changed.

Abstract: A noise cancellation circuit for use with a digital signal includes a plurality of equally weighted cells (53) for providing an analogue output signal (35) in dependence upon the value of the digital signal. A switching arrangement (51) dynamically switches a number of the plurality of cells according to a sequencing scheme, which comprises a first sequence arranged to switch each of the plurality of cells (53) an equal number of times, and a second sequence arranged to define one of the plurality of cells (53) as a starting position for the first sequence. In this way low frequency tone generation within the analogue output signal is substantially eliminated.

Abstract: A phase locked loop PLL has a current controlled oscillator ICO, having an input resistance Rin. Rin is proportional to a control current Idac sent to ICO. ICO is coupled to a capacitor, the capacitor and Rin introduce a pole Fpole in the transfer function of PLL. The PLL further has a sigma delta modulator, for providing a digital sigma delta modulated control signal SDO, SDO is converted to an analog control current Idac, that is provided to ICO and smoothed by Rin and the capacitor. The sigma delta modulator forces error signal outside a predetermined frequency BWsd; and Fpole tracks BWsd.

Abstract: A circuit arrangement (100) is coupled to a resistor (150) having at least two portions (110, 120). The arrangement (100) provides a substantially linear performance of the resistor (150). The arrangement (100) comprises a differential difference amplifier (160) (with input stages (170, 180) and output stage (190)) and a feedback unit (130). The input stages (170, 180) modify first (161) and second (162) measurement signals (e.g., (V.sub.B -V.sub.A) and (V.sub.A -GND), respectively) from the resistor portions (110, 120) to intermediate signals (OPH, OMH, OPL, OML). The output stage (190) differentially amplifies sums (at nodes 191, 192) of the intermediate signals and provides a control signal (CONTROL) which corresponds to a magnitude difference between the first and second measurement signals. The feedback unit (130) receives the control signal and supplies a corrective current (I) to the resistor (150) to offset non-linearity.

Abstract: A digital-to-analog converter (200) has a first portion (208) which receives a digital input signal X (201') and has serially coupled a second portion (209) which provides an analog output signal Y (202'). The first portion (208) is a delta-sigma modulator with integrators (210 and 215), adders (203 and 205), a comparator (220) and delay stages (230 and 235). The second portion (209) comprises a commutator (260), unit converters (280-n) and an analog adder (290). In the second portion, the unit converters (280-n) can be mismatched. The first portion (208) provides a noise-shaped intermediate signal V (221') which has substantially zero noise at that frequencies where the mismatches would lead to unwanted spectral tones.

Abstract: A circuit (200) comprises transistors (240, 250, 260), an operational amplifier (270) and serially coupled resistors (210, 220). The circuit (200) is coupled to reference lines (201, 202). An input voltage V.sub.X on an input terminal (203) is applied across the resistors (210, 220) and divided to an output voltage V.sub.Y on an output terminal (204). Output voltage V.sub.Y is measured (as V.sub.M) by the operational amplifier (270). The operational amplifier (270) controls a current I.sub.A in a first current path between the reference lines (201, 202). The current I.sub.A is mirrored to a current I.sub.S in a second current path through the resistors (210, 220). The current I.sub.S is generated by one of the transistors (260) and substantially proportional to the input voltage V.sub.X. Therefore, the resistors (210, 220) do not substantially load the input and the circuit (200) exhibits a high input impedance.

Abstract: A current source (200) comprises an input bias unit (291), a transconductance unit (295), an output bias unit (292), a combiner unit (296) and a voltage source 130'. In the transconductance unit (295), a first current mirror (215) provides currents I.sub.A and I.sub.B which are distributed to cross-coupled first and second transistors arrangements (TA 3 and TA 4). The first arrangements (TA 3) receives a control signal (V.sub.GS12) which is derived from a master signal (205') at a master terminal (205). The second arrangement (TA 4) is controlled from the first arrangement (TA 3). The transconductance ratio between the arrangements (TA 3 and TA 4) is regulated through a feedback in a second current mirror (235). A transconductance drift is substantially prevented. Output currents which are related to this stabilized transconductance ratio are provided at output terminals (203, 204). A first output current (I.sub.out1) is derived from the second arrangement (TA 3) and a second output current (I.sub.

Abstract: An I/O circuit whose output receives a voltage V.sub.PAD which is temporarily higher than a critical voltage V.sub.DS MAX >V.sub.DS 1 across drain and source of a conducting first N-FET (110, N1) acting as a pull-down device. The first N-FET is protected against hotelectron induced degradation by a serially coupled second N-FET (130, N3). A variable drain-source voltage V.sub.DS 3 is added to V.sub.DS 1. A comparator (150) compares the received voltage V.sub.PAD to a supply voltage V.sub.CC and pulls a gate (G) of the second N-FET (N3) to V.sub.PAD or to V.sub.CC. The conductivity of the second N-FET (N3) is thereby changed so that VPAD is distributed among V.sub.DS 1 and V.sub.DS 2. The comparator (150) conveniently comprises two P-FETs (P1, P2, 160, 170).

Abstract: In a circuit (200), a differential pair (217/227) of transistors (210 and 220) receives a differential input signal (X.sub.1 -X.sub.2) from input terminals (211 and 221) and provides a differential output signal (Y.sub.1 -Y.sub.2) to output lines (215 and 225). The differential pair (217/227) is powered from a common constant current source (290) at a common node (205). Nonlinearities, such as cubic terms in a transfer function H=(Y.sub.1 -Y.sub.2)/(X.sub.1 -X.sub.2) caused by the transistors are compensated by compensation circuits (237 and 247). The compensation circuits (237 and 247) are coupled between the node (205) and the output lines (215 and 225). The compensation circuits (237 and 247) are controlled by the input signal (X.sub.1 -X.sub.2) and drain current from the node (205). Thereby, the currents going into the transistors (210 and 220) and the transistors gains (Y.sub.1 /X.sub.1 and Y.sub.2 /X.sub.2) are modified, so that nonlinearities are substantially canceled.

Abstract: A reference circuit (200') has bipolar transistors (216, 226) providing a voltage difference .DELTA.V of base-emitter voltages .vertline.V.sub.BE .vertline. and has resistors (210/R.sub.1, 220/R.sub.2) for adding a current I.sub.R1 resulting from .DELTA.V and a current I.sub.R2 resulting from of base-emitter voltage .vertline.V.sub.BE .vertline. of one bipolar transistor (216 or 226) so that a resulting temperature coefficient TC.sub.TOTAL of said currents I.sub.R1 and I.sub.R2 is compensated. The circuit (200') has voltage transfer units (260, 270) which transfer .DELTA.V to the resistors (210/R.sub.1, 220/R.sub.2) so that the resistors (210/R.sub.1, 220/R.sub.2) do not substantially load the bipolar transistors (216, 226). The voltage transfer units (260, 270) have input stages with n-channel FETs. A control unit (241) which is coupled to the bipolar transistors (216, 226) adjusts input voltages (.vertline.V.sub.CE .vertline.

Abstract: A frequency divider (50) comprises complementary components (e.g., CMOS transistors) which are placed in two complementary portions (10, 20) with similar structures. The portions are coupled by four lines (131-134). Each line (e.g., 131) is coupled to a pair of transistors including a pull device (e.g., 271) and a hold device (e.g., 291). The devices receives identical signals from another line (e.g., 134) and the input signal X in the same, non-inverted form. The devices have complementary logical functions because of their complementary structures (serial.backslash.parallel) and complementary components (P-FET, N-FET). When a line (e.g., 131) is pulled to a reference line (e.g., 91), contention between the devices is substantially avoided. There is no need to provide the input signal X in a non-inverted and in an inverted form.

Abstract: A MOS switching circuit (1) for providing constant signal-independent gate-to-source voltage at a switching transistor (2) of a differential switched capacitor circuit so that a signal-independent resistance is provided between its source and drain includes a first control transistor (5) coupled between the input (3) and the gate of the switching transistor (2). The gate of switching transistor (2) is also coupled to a first clock phase signal PHI1 and the gate of the first control transistor (5) is coupled to a second, non-overlapping clock phase signal PHI2. A second control transistor (6) is coupled between the input (3) and the second clock phase signal PHI2 and its gate is coupled to the first clock phase signal PHI1. Capacitors (7) and (8) are coupled between the transistors (2, 5 and 6) and the clock phase signals PHI1 and PHI2, respectively.

Abstract: The rise time of a voltage Vo presented to a load, based on an input voltage Vi provided via an RC filter coupled to the load for removing higher frequency noise on Vo, is substantially reduced by providing a sensor circuit with differential inputs Vi, Vo. The sensor circuit drives a charger circuit coupled to a DC potential and the load so that rapid charging of C to Vo does not depend on R. As Vo approaches Vi, the sensor circuit deactivates the charger circuit to stop further charging and a latch coupled to the sensor circuit shuts off the sensor circuit to reduce power consumption while (Vo.about.Vi)>0. A current mirror buffer is desirably included between the sensor output and the latch for level shifting.

Abstract: An analog-to-digital converter (100) has a first path (110) with a first sigma-delta modulator (114) which transforms an analog input signal X.sub.0 (111') from an input terminal (101) to a digital output signal Y.sub.0 at an output terminal (102). In a second path (120), a digital dither signal D (121') is combined with a digital intermediate signal Z.sub.0 (115') from the first modulator (114) and digitally processed by a second sigma-delta modulator (124) to an intermediate signal Y.sub.1 (125') Y.sub.1 is fed to the first modulator (114) and to the output terminal (102) with opposite sign ("+" and "-", respectively). Thereby, multipliers (133 and 127) attenuate Y.sub.1. The dither signal D (121') is used substantially only within the converter (100), and is substantially canceled before the output terminal (102). This features preserve a high SNR of the converter (100) and low spectral tones in output signal Y.sub.0.