Abstract: An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions.

Abstract: A two stage operational amplifier circuit comprises a first stage (31) having an input (2, 4) and an output, and a second stage (33) having an input and an output (19). The second stage input is coupled to receive the first stage output. A feedback path (41, 45, 47, 51) is coupled between the output and the input of the second stage. The feedback path (41, 45, 47, 51) comprises a low-frequency compensation path (41, 45) and high-frequency compensation path (45, 47, 51). The feedback path (41, 45, 47, 51) is compensated such that the frequency response of the second output of the second stage is substantially 6 dB per octave throughout the high-frequency region.

Abstract: The amplifier (200) includes an input stage (220) coupled to two output transistors (281, 282) having a common terminal at the output terminal (206) of the amplifier. Class AB operation of the output transistors (281, 282) is possible at a comparatively low supply voltage. In order to obtain such operation, measurement transistors (271, 272) are coupled to the same control input (283, 284) as the output transistors (281, 282). These measurement transistors (271, 272) are serially coupled to a current mirror (260). The quiescent current of the output transistors (281, 282) is measured and used to produce a feedback signal which is superimposed to the control signals.

Abstract: The intermediate frequency (IF) amplifier (10) of the invention comprises a differential stage (40) having transistors (41, 42) serially coupled to inductive loads (31, 32). There is only one point at common sources (node 45) which is sensitive to spikes. A feedback stage (60) extracts a common mode spike component at spike frequency (f.sub.S) from the output and returns a feedback signal to the sensitive point (node 45). Comparing to traditional differential amplifiers, the common mode rejection at resonance frequencies (f.sub.R) can be 30 times higher. This makes the amplifier (10) spike insensitive and suitable for the integration into mixed analog-digital chips, such as DSP chips, where the analog portions operate in the same frequency range as the digital portions.

Abstract: An analog-to-digital converter is introduced which operates as an oversampled delta-sigma converter. The converter is implemented fully differentially, having doubled integrator capacitors (130, 230), comparators (180, 280), and feedback units (160, 260). In order to reduce the influence of parasitic capacities, the feedback units (160, 260) comprise cascoded switches (171-179). Internal auxiliary signals for controlling the feedback units (160, 260) return to zero at clock frequency. The converter can be used in an integrated signal processing circuit having analog and digital domains on one chip. The capacitors (130, 230) itself are implemented by MOS transistors with the same single poly process as the rest of the circuit. In a second embodiment of the invention, the analog-to-digital converter (500) comprises multiple comparators (580, 572, 573, 574), dynamic matching circuits (801, 802). The comparators (572, 573, 574) can received dithered input signals.

Abstract: A linear voltage-to-current converter (VIC) 100 for converting a differential input voltage V.sub.D into a differential output current ID is provided. The VIC (100) comprises a main stage (20) and a correction stage (30) having two FET each. Every stage is fed by a separate current source (150, 160). In two nodes (174, 172) the output currents of the stages are added. The scale factors k.sub.1 and k.sub.3 of the FET are coordinated so that distortions are reduced.

Abstract: A high frequency monolithic amplifier (100) is provided which can be used, for example, in the PLL prescaler of cellular radio systems. The amplifier (100) amplifies single-ended signals having a frequency in the GHz area. It includes a feedback unit (160) which uses parasitic capacitors. The feedback depends on the frequency and is positive for high frequencies and negative for low frequencies. A high gain can be obtained for high frequencies. A comparative low gain a low frequencies prevents the propagation of noise. The amplifier (100) of the present invention can be cascaded to an, for example, 3 stage amplifier arrangement (300).

Abstract: A differential-to-single-ended converter comprising a resistor network (205) and an operational amplifier is introduced. In comparison to prior art converters, a resistor (250) placed between the non-inverting input (264) of the operational amplifier (260) and the negative input terminal (202) of the converter (200). The common mode voltage (V.sub.nii ') at the non-inverting input (264) does not depend on the differential input voltage (V.sub.in.sup.#) of the converter (200) and has low fluctuations. This allows the use of an operational amplifier (260) with low CMRR and makes the converter (200) suitable for low voltage applications.

Abstract: A digital-to-analog (D/A) converter (400) receives a N bit digital signal S.sub.N by a signal divider (440) which divides it into digital group signals S.sub.Nk. In converter blocks (401.sub.k), these digital group signals S.sub.Nk are then separately converted into analog group signals S.sub.Gk. In a summation circuit (460) these analog group signals S.sub.Gk are combined to the analog signal S.sub.A. The converter blocks (401.sub.k) can comprise banks (430.sub.k) with, e.g., current sources whose currents I.sub.i are combined into the analog group signal S.sub.Gk selectively according to the digital group signal S.sub.Nk. The converter blocks (401.sub.k) can include circuits to equalize component variations, such as dynamic matching circuits (480.sub.k). The converter blocks (401.sub.k) can be configured according to the significance of the digital group signals S.sub.Nk and the hardware can be optimized.

Abstract: The present invention describes a bias generator (10) which supplies a temperature stabilizing bias current (72) to a main circuit (90). The bias generator (10) comprises a measurement unit (20) having a similar structure and temperature characteristic as the main circuit (90). Measurement unit (20) supplies a temperature dependent measurement signal (27). A temperature invariant element (40) supplies a temperature independent reference signal (47). These signals (27, 47) are compared in a differential amplifier (30) which controls variable current sources (50, 60, 70). The variable current sources (50, 60) supply the measurement unit (20), the temperature invariant element (40) and the bias current (72) for the main circuit (90) itself. A negative feedback is produced which results in a stabilized transconductance of the main circuit (90). Therefore, the bias current (72) which determines all other currents and the speed of the main circuit (90) is automatically adjusted to the needs.

Abstract: Oscillation of the output (16, 17) of an integrated circuit output buffer (43) is automatically damped by sensing ground lead (18) transients as the buffer output (16, 17) changes, and when the ground lead (18) swing is large enough, using the sensed change to apply a turn-off signal of the appropriate polarity to a transistor (N1) serially placed in the output buffer (43) to add resistance during the transition. The added resistance damps out the oscillations quickly to prevent rebound of the buffer output voltage past the logic transition threshold (Vol). An RC time constant (R1, C1) controls the duration of the added resistance which disappears after the transition is complete. The action of a damping control circuit (45) is speed dependent so that greater damping is provided for fast transitions when oscillations would be more sever and no damping during slow transitions when damping is not needed.

Abstract: A noise cancelling circuit (10) is used with a D/A converter, the converter including a first modulator (11) and a data output. The circuit (10) has an error measuring arrangement (12, 13, 14) for measuring a quantization error signal of the modulator (11). A filter (19) receives the error signal end provides a fired error signal. A filter compensator (17) is coupled to the data output and provides a compensated output. A scaler (15) is coupled to receive the filtered error signal and provides a scaled filtered error signal. A second modulator (16) is coupled to receive the scaled filtered error signal and provides a single bit stream of error data. A summing arrangement (18) sums the single bit stream of error data and the compensated output from the first modulator and provides a corrected output, such that the error signal is filtered, sealed and modulated end the data output is compensated such that the corrected output is obtained having a substantially reduced quantization error.

Abstract: An apparatus and method for performing adaptive power regulation for an integrated circuit. The present invention utilizes a voltage regulator circuit (16) to regulate the voltage provided to an integrated circuit core (12), and to thereby reduce the power consumption of the integrated circuit core (12). In one form, the voltage regulator circuit (16) utilizes two voltage converting mechanisms, namely an inductive converter (22) and a resistive converter (24). The inductive converter (22) and the resistive converter (24) supplement each other in order to supply the current required by integrated circuit core (12). All or a portion of voltage regulator (16) may be located on the same integrated circuit substrate as integrated circuit core (12).

Abstract: A switched capacitor differential circuit switches first and second differential input signals (Vinp1, Vinp2) to respective inputs (A, B) of an operational amplifier (12) via respective first and second signal paths. Each signal path includes a coupling capacitor (13, 14) and two switching devices (2, 3 and 4, 5) to switch the input signals to charge the capacitors at a first phase of a clock signal and to discharge the capacitors onto the inputs of the amplifier at a second phase of the clock signal. In order to remove common mode spikes from transferring to the amplifier, a pair of comon mode capacitors (16, 17) are coupled between the inputs and a common node (15), which is coupled via a pair of switches (6, 7) to the first and second signal paths between the capacitors and the second of the switching devices so that the coupling capacitors are discharged relative to the common node.

Abstract: A transition control circuit (2) for controlling the transitions of an output signal, at an output node (8) of a driver circuit, in dependence on the logic state of an input signal at an input node (10). The output signal being switchable between a first logic state and a second logic state. The transition control circuit (2) comprises first means (16) and second means (14). The first means (16) is enabled when the output signal has the first logic state and the input signal has the second logic state, and is disabled when the output signal has the second logic state or the input signal has the first logic state. Once enabled, the first means (16) couples the output node (8) to a first supply line (GNDA) whereby the output signal switches to the second logic state. The second means (14) is enabled when the output signal has the second logic state and the input signal has the second logic state, and is disabled when the output signal has the first logic state or the input signal has the first logic state.

Abstract: A compensating circuit (8) is used with a switched capacitor circuit (10) which includes a switched capacitor arrangement (12) and an op-amp (1) having a first input (14) coupled to a switched capacitor (11), a second input and an output (16). A sampling circuit (19,17,23) samples an error signal at the first input (14) of the op-amp (1) and an amplifier (15) coupled to receive the sampled error signal provides a compensation signal in dependence upon the sampled error signal. The compensation signal provides an offset signal for the second input of the op-amp (1), such that propagation of the error signal to the output (16) of the op-amp (1) is substantially reduced.

Abstract: An integrated circuit structure for use in identifying a value of an analog signal includes a central processing unit that executes instructions to perform data processing operations. The data processing operations include a successive approximation analog-to-dialog conversion operation to provide a digital value based upon an input data signal. A pulse with modulation (PWM) element converts the digital value to a square-wave output signal having a duty cycle corresponding to the digital value. A PWM element is adapted for connection to a low pass filter such that the square-wave output signal is provided as an input to the low pass filter. The low pass filter provides an output analog signal corresponding to the duty cycle of the square-wave output signal. An input port is adapted for connection to an output of a comparator. The comparator receives as inputs the output analog signal the low pass filter and the analog signal.

Abstract: An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions.

Abstract: A driver circuit (8) is arranged to switch a transistor (10) of a switched capacitor circuit, or transistors (62 and 64) of a differential switched capacitor circuit, between a first state, in which the transistor switch is closed whereby an input signal (VINP) is transferred to an output, and a second state, in which the transistor switch is open. The driver circuit includes a maximum and a minimum selection (12, 14) between the input signal and a reference voltage (VAG) , a voltage shift element (26), and switches (16, 18, 20, 22, 24), coupled to receive the input signal (VINP) and to the gate electrode of the transistor switch (10), which ensures that the gate-to-source voltage of the transistor switch (10), in the first and second states, is independent of the input signal (VINP).

Abstract: An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions.