Abstract: A memory device includes a stack of alternating word line layers and insulating layers over a substrate. The word line layers includes a bottom select gate (BSG) positioned over the substrate. The memory device includes first dielectric trenches that are formed in the BSG of the word line layers and extend in the length direction of the substrate to separate the BSG into a plurality of sub-BSGs. The memory device also includes a first common source region (CSR) that is formed over the substrate and extends in the length direction of the substrate. The first CRS further extends through the word line layers and the insulating layers in a height direction of the substrate, where the first CSR is arranged between two adjacent first dielectric trenches of the first dielectric trenches.

Abstract: A 3D memory device may include a first set of memory layers, a second set of memory layers above the first set of memory layers, and a first dummy memory layer between the first and second memory layers. The 3D memory device may include a plurality of NAND memory strings each extending through the first and second set of memory layers and the first dummy memory layer. The 3D memory device may include a word line (WL) driving circuit that, when programming one of the first set of memory layers, may be configured to apply a second pre-charge voltage to the first dummy memory layer during the pre-charge period. The second pre-charge voltage may overlap with the first pre-charge voltage and ramp down prior to the first pre-charge voltage.

Abstract: In a method for manufacturing a memory device, a plurality of first insulating layers and a bottom select gate (BSG) layer are formed over a substrate, where the first insulating layers are disposed between the substrate and the BSG layer. One or more first dielectric trenches are formed to pass through the BSG layer and the first insulating layers, and extend in a length direction of the substrate. A plurality of word line layers and a plurality of second insulating layers are formed over the BSG layer, where the second insulating layers are disposed between the BSG layer and the word line layers. One or more common source regions are formed over the substrate to extend in the length direction of the substrate, and further extend through the BSG layer, the first insulating layers, the word line layers, and the second insulating layers.

Abstract: A memory device includes a memory array including memory strings. Each memory string includes a plurality of top memory cells, a plurality of bottom memory cells, and one or more dummy memory cells between the top memory cells and the bottom memory cells. The memory device also includes a plurality of word lines respectively coupled to gate terminals of the top memory cells and the bottom memory cells. The memory device further includes a control circuit configured to provide a control signal to control programming a target memory cell of the top memory cells. The gate terminal of the target memory cell are coupled to a selected word line of the word lines.

Abstract: A 3D memory device may include a first set of memory layers, a second set of memory layers above the first set of memory layers, and a first dummy memory layer between the first and second memory layers. The 3D memory device may include a plurality of NAND memory strings each extending through the first and second set of memory layers and the first dummy memory layer. The 3D memory device may include a word line (WL) driving circuit that, when programming one of the first set of memory layers, may be configured to apply a second pre-charge voltage to the first dummy memory layer during the pre-charge period. The second pre-charge voltage may overlap with the first pre-charge voltage and ramp down prior to the first pre-charge voltage.

Abstract: A three-dimensional (3D) memory device may include a first set of memory layers, a second set of memory layers above the first set of memory layers, and a first dummy memory layer between the first and second sets of memory layers. The 3D memory device may further include a peripheral circuit that includes a word line (WL) driving circuit configured to when programming a first memory layer of the first set of memory layers, apply a first pre- charge voltage to the first dummy memory layer during a pre-charge period associated with the first memory layer, and when programming a second memory layer of the first set of memory layers located above the first memory layer, apply a second pre-charge voltage to the first dummy memory layer during a pre-charge period associated with the second memory layer. The first pre-charge voltage may be larger than the second pre-charge voltage.

Abstract: The present disclosure relates to a three-dimensional memory (3D) and a control method thereof. The 3D memory includes a first deck and a second deck which are stacked in a vertical direction of a substrate. The first deck and the second deck each includes a plurality of memory string. Each memory string includes a plurality of memory cells. The plurality of memory cells includes a first portion and a second portion. A diameter of channel structure corresponding to the first portion of memory cells is smaller than that of channel structure corresponding to the second portion of memory cells. The method includes performing a read operation for selected memory cells that are in at least one of the first deck or the second deck; and applying a pass voltage to non-selected memory cells other than the selected memory cells in the first deck and the second deck. A first pass voltage is lower than a second pass voltage.

Abstract: A vertical NAND string in a channel-stacked 3D memory device may be programmed using ISPP scheme, wherein a preparation step is introduced immediately after each verification step and before the start of a corresponding verification step. During the preparation step, the electrons accumulated in the channel may be drained by the selected bit line for enhancing the coupling effect of the channel, thereby reducing program disturb and increasing program speed.

Abstract: In a memory device which includes a plurality of memory cells, a top dummy storage region, a bottom dummy storage region, a plurality of word lines and a plurality of bit lines form in a substrate, a selected bit line among the plurality of bit lines, a channel region in the substrate and a source region in the substrate are pre-charged and a negative pre-pulse voltage is applied to the bottom dummy storage region during a first period. A selected memory cell among the plurality of memory cells is programmed during a second period subsequent to the first period, wherein the selected memory cell is coupled to the selected bit line and a selected word line among the plurality of word lines.

Abstract: A memory includes a first deck including a first set of word lines, a second deck above the first deck and including a second set of word lines, and a controller. The controller is configured to apply a program voltage to a first target word line of the first set of word lines in the first deck, and apply a first pass voltage to at least one of the first set of word lines that is below the first target word line when applying the program voltage to the first target word line. The controller is also configured to apply the program voltage to a second target word line of the second set of word lines in the second deck, and apply a second pass voltage to at least one of the second set of word lines that is below the second target word line when applying the program voltage to the second target word line. The second pass voltage is greater than the first pass voltage.

Abstract: A memory includes a first portion, a second portion and a controller. The first portion includes a first word line to a kth word line. The second portion is formed above the first portion and includes a (k+1)th word line to an mth word line. When an xth word line is used to perform a program operation, the controller is used to apply a first voltage to the first word line to an (x?2)th word line, a second voltage to an (x?1)th word line, and a third voltage to an (x+1)th word line. x, k and m are positive integers.

Abstract: A memory device includes a memory array including memory strings. Each memory string includes a plurality of top memory cells, a plurality of bottom memory cells, and one or more dummy memory cells between the top memory cells and the bottom memory cells. The memory device also includes a plurality of word lines respectively coupled to gate terminals of the top memory cells and the bottom memory cells, and one or more dummy word lines respectively coupled to gate terminals of the one or more dummy memory cells. The memory device further includes a control circuit configured to program a target memory cell coupled to a selected word line of the plurality of word lines. To program the target memory cell, the control circuit is configured to apply a biased dummy word line pre-pulse signal to the one or more dummy word lines in a pre-charge period prior to a programming period.

Abstract: A memory includes a first portion, a second portion and a controller. The first portion includes a first word line to a kth word line. The second portion is formed above the first portion and includes a (k+1)th word line to an mth word line. When an xth word line is used to perform a program operation, the controller is used to apply a first voltage to the first word line to an (x?2)th word line, a second voltage to an (x?1)th word line, and a third voltage to an (x+1)th word line. x, k and m are positive integers.

Abstract: A vertical NAND string in a channel-stacked 3D memory device may be programmed using ISPP scheme, wherein a preparation step is introduced immediately after each verification step and before the start of a corresponding verification step. During the preparation step, the electrons accumulated in the channel may be drained by the selected bit line for enhancing the coupling effect of the channel, thereby reducing program disturb and increasing program speed.

Abstract: A memory includes a first portion, a second portion and a controller. The first portion includes a first word line to a kth word line. The second portion is formed above the first portion and includes a (k+1)th word line to an mth word line. When an xth word line is used to perform a program operation, the controller is used to apply a first voltage to the first word line to an (x?2)th word line, a second voltage to an (x?1)th word line, and a third voltage to an (x+1)th word line. x, k and m are positive integers.

Abstract: Embodiments of 3D memory devices and methods for operating the 3D memory devices are disclosed. In an example, a method for operating a 3D memory device is disclosed. The 3D memory device includes a plurality of memory decks each including a plurality of memory layers in a vertical direction, and a plurality of first dummy memory layers between the first and second memory decks in the vertical direction. Each memory layer in a first memory deck of the plurality of memory decks is first programmed. The first programming includes applying a program voltage to the memory layer and a channel pass voltage smaller than the program voltage to each of the rest of the memory layers in the first memory deck. Each memory layer in a second memory deck of the plurality of memory decks above the first memory deck is second programmed. The second programming includes applying the program voltage to the memory layer and the channel pass voltage to each of the rest of the memory layers in the second memory deck.

Abstract: A memory includes an upper deck and a lower deck. The upper deck includes a first upper dummy word line. The lower deck includes a first lower dummy word line. A method for reducing program disturbance of the memory includes adjusting a first upper bias voltage applied to the first upper dummy word line and/or a first upper threshold voltage of the first upper dummy word line to adjust a first difference between the first upper bias voltage and the first upper threshold voltage; and adjusting a first lower bias voltage applied to the first lower dummy word line and/or a first lower threshold voltage of the first lower dummy word line to adjust a second difference between the first lower bias voltage and the first lower threshold voltage.

Abstract: In a memory device which includes a plurality of memory cells, a top dummy storage region, a bottom dummy storage region, a plurality of word lines and a plurality of bit lines form in a substrate, a selected bit line among the plurality of bit lines, a channel region in the substrate and a source region in the substrate are pre-charged and a negative pre-pulse voltage is applied to the bottom dummy storage region during a first period. A selected memory cell among the plurality of memory cells is programmed during a second period subsequent to the first period, wherein the selected memory cell is coupled to the selected bit line and a selected word line among the plurality of word lines.

Abstract: A memory device includes a memory array including memory strings. Each memory string includes a plurality of top memory cells, a plurality of bottom memory cells, and one or more dummy memory cells between the top memory cells and the bottom memory cells. The memory device also includes a plurality of word lines respectively coupled to gate terminals of the top memory cells and the bottom memory cells. The memory device further includes a control circuit configured to provide a control signal to control programming a target memory cell of the top memory cells. The gate terminal of the target memory cell are coupled to a selected word line of the word lines.

Abstract: A memory device includes a memory array including memory strings. Each memory string includes a plurality of top memory cells, a plurality of bottom memory cells, and one or more dummy memory cells between the top memory cells and the bottom memory cells. The memory device also includes a plurality of word lines respectively coupled to gate terminals of the top memory cells and the bottom memory cells, and one or more dummy word lines respectively coupled to gate terminals of the one or more dummy memory cells. The memory device further includes a control circuit configured to program a target memory cell coupled to a selected word line of the plurality of word lines. To program the target memory cell, the control circuit is configured to apply a biased dummy word line pre-pulse signal to the one or more dummy word lines in a pre-charge period prior to a programming period.