Abstract: When programming and verifying a memory device which includes a plurality of memory cells and a plurality of word lines, a first coarse programming is first performed on a first memory cell among the plurality of memory cells which is controlled by a first word line among the plurality of word lines, and then a second coarse programming is performed on a second memory cell among the plurality of memory cells which is controlled by a second word line among the plurality of word lines. Next, a first coarse verify current is used for determining whether the first memory cell passes a coarse verification and a second coarse verify current is used for determining whether the second memory cell passes a second coarse verification, wherein the second coarse verify current is smaller than the first coarse verify current.

Abstract: A memory device includes a stack of alternating word line layers and insulating layers over a substrate. The word line layers includes a bottom select gate (BSG) positioned over the substrate. The memory device includes first dielectric trenches that are formed in the BSG of the word line layers and extend in the length direction of the substrate to separate the BSG into a plurality of sub-BSGs. The memory device also includes a first common source region (CSR) that is formed over the substrate and extends in the length direction of the substrate. The first CRS further extends through the word line layers and the insulating layers in a height direction of the substrate, where the first CSR is arranged between two adjacent first dielectric trenches of the first dielectric trenches.

Abstract: In a method for manufacturing a memory device, a plurality of first insulating layers and a bottom select gate (BSG) layer are formed over a substrate, where the first insulating layers are disposed between the substrate and the BSG layer. One or more first dielectric trenches are formed to pass through the BSG layer and the first insulating layers, and extend in a length direction of the substrate. A plurality of word line layers and a plurality of second insulating layers are formed over the BSG layer, where the second insulating layers are disposed between the BSG layer and the word line layers. One or more common source regions are formed over the substrate to extend in the length direction of the substrate, and further extend through the BSG layer, the first insulating layers, the word line layers, and the second insulating layers.

Abstract: In a memory device which includes a plurality of memory cells, a top dummy storage region, a bottom dummy storage region, a plurality of word lines and a plurality of bit lines form in a substrate, a selected bit line among the plurality of bit lines, a channel region in the substrate and a source region in the substrate are pre-charged and a negative pre-pulse voltage is applied to the bottom dummy storage region during a first period. A selected memory cell among the plurality of memory cells is programmed during a second period subsequent to the first period, wherein the selected memory cell is coupled to the selected bit line and a selected word line among the plurality of word lines.

Abstract: In a memory device which includes a plurality of memory cells, a top dummy storage region, a bottom dummy storage region, a plurality of word lines and a plurality of bit lines form in a substrate, a selected bit line among the plurality of bit lines, a channel region in the substrate and a source region in the substrate are pre-charged and a negative pre-pulse voltage is applied to the bottom dummy storage region during a first period. A selected memory cell among the plurality of memory cells is programmed during a second period subsequent to the first period, wherein the selected memory cell is coupled to the selected bit line and a selected word line among the plurality of word lines.

Abstract: A memory includes an upper deck and a lower deck. The upper deck includes a first upper dummy word line. The lower deck includes a first lower dummy word line. A method for reducing program disturbance of the memory includes adjusting a first upper bias voltage applied to the first upper dummy word line and/or a first upper threshold voltage of the first upper dummy word line to adjust a first difference between the first upper bias voltage and the first upper threshold voltage; and adjusting a first lower bias voltage applied to the first lower dummy word line and/or a first lower threshold voltage of the first lower dummy word line to adjust a second difference between the first lower bias voltage and the first lower threshold voltage.

Abstract: Embodiments of 3D memory devices and methods for operating the 3D memory devices are disclosed. In an example, a method for operating a 3D memory device is disclosed. The 3D memory device includes a plurality of memory decks each including a plurality of memory layers in a vertical direction, and a plurality of first dummy memory layers between the first and second memory decks in the vertical direction. Each memory layer in a first memory deck of the plurality of memory decks is first programmed. The first programming includes applying a program voltage to the memory layer and a channel pass voltage smaller than the program voltage to each of the rest of the memory layers in the first memory deck. Each memory layer in a second memory deck of the plurality of memory decks above the first memory deck is second programmed. The second programming includes applying the program voltage to the memory layer and the channel pass voltage to each of the rest of the memory layers in the second memory deck.

Abstract: A method of performing a programming operation to a three dimensional (3D) NAND memory device is disclosed. The method makes residual electrons trapped in storage regions of middle dummy memory cells of an unselected string of the 3D NAND memory device to be removed during the pre-charging phase, so as to reduce program disturb to an selected string which neighbors the unselected string.

Abstract: A non-volatile memory device is disclosed. The non-volatile memory device includes a memory array, a plurality of word lines, a plurality of dummy word lines, a first control circuit and a second control circuit. The plurality of word lines are connected to a plurality of top memory cells and bottom memory cells of a memory string of the memory array. The plurality of dummy word lines are connected to a plurality of dummy memory cells connected between the plurality of top memory cells and bottom memory cells. The first control circuit is configured to apply a bit line pre-pulse signal to the bit line during a pre-charge period. The second control circuit is configured to apply a selected word line signal to a selected word line, apply an unselected word line signal to unselected word lines and apply a negative pre-pulse signal to the plurality of dummy word lines.

Abstract: A 3D-NAND memory device is provided. The memory device includes a substrate, a bottom select gate (BSG) disposed over the substrate, a plurality of word lines positioned over the BSG with a staircase configuration and a plurality of insulating layers disposed between the substrate, the BSG, and the plurality of word lines. In the disclosed memory device, one or more first dielectric trenches are formed in the BSG and extend in a length direction of the substrate to separate the BSG into a plurality of sub-BSGs. In addition, one or more common source regions are formed over the substrate and extend in the length direction of the substrate. The one or more common source regions further extend through the BSG, the plurality of word lines and the plurality of insulating layers.

Abstract: When programming and verifying a memory device which includes a plurality of memory cells and a plurality of word lines, a first coarse programming is first performed on a first memory cell among the plurality of memory cells which is controlled by a first word line among the plurality of word lines, and then a second coarse programming is performed on a second memory cell among the plurality of memory cells which is controlled by a second word line among the plurality of word lines. Next, a first coarse verify current is used for determining whether the first memory cell passes a coarse verification and a second coarse verify current is used for determining whether the second memory cell passes a second coarse verification, wherein the second coarse verify current is smaller than the first coarse verify current.

Abstract: Embodiments of 3D memory devices and methods for operating the 3D memory devices are disclosed. In an example, a method for operating a 3D memory device is disclosed. The 3D memory device includes memory decks each including memory layers in a vertical direction. Each memory layer in a first memory deck is first programmed. The first programming includes applying a program voltage to the memory layer and a first channel pass voltage smaller than the program voltage to each rest of the memory layers. Each memory layer in a second memory deck above the first memory deck is second programmed. The second programming includes applying the program voltage to the memory layer and the first channel pass voltage to each rest of the memory layers. The second programming further includes applying a second channel pass voltage smaller than the first channel pass voltage to each memory layer in the first memory deck.

Abstract: A method of performing a programming operation to a three dimensional (3D) NAND memory device is disclosed. The method makes residual electrons trapped in storage regions of middle dummy memory cells of the unselected string of the 3D NAND memory device to be removed during the pre-charging phase, so as to reduce program disturb to the selected string which neighbors the unselected string.

Abstract: Embodiments of 3D memory devices and methods for operating the 3D memory devices are disclosed. In an example, a method for operating a 3D memory device is disclosed. The 3D memory device includes memory decks each including memory layers in a vertical direction. Each memory layer in a first memory deck is first programmed The first programming includes applying a program voltage to the memory layer and a first channel pass voltage smaller than the program voltage to each rest of the memory layers. Each memory layer in a second memory deck above the first memory deck is second programmed The second programming includes applying the program voltage to the memory layer and the first channel pass voltage to each rest of the memory layers. The second programming further includes applying a second channel pass voltage smaller than the first channel pass voltage to each memory layer in the first memory deck.

Abstract: A 3D-NAND memory device is provided. The memory device includes a substrate, a bottom select gate (BSG) disposed over the substrate, a plurality of word lines positioned over the BSG with a staircase configuration and a plurality of insulating layers disposed between the substrate, the BSG, and the plurality of word lines. In the disclosed memory device, one or more first dielectric trenches are formed in the BSG and extend in a length direction of the substrate to separate the BSG into a plurality of sub-BSGs. In addition, one or more common source regions are formed over the substrate and extend in the length direction of the substrate. The one or more common source regions further extend through the BSG, the plurality of word lines and the plurality of insulating layers.