Abstract: Provided are a semiconductor device and a method for manufacturing the same, and a semiconductor package. The semiconductor device includes a die stack and a cap substrate. The die stack includes a first die, second dies stacked on the first die, and a third die stacked on the second dies. The first die includes first through semiconductor vias. Each of the second dies include second through semiconductor vias. The third die includes third through semiconductor vias. The cap substrate is disposed on the third die of the die stack. A sum of a thickness of the third die and a thickness of the cap substrate ranges from about 50 ?m to about 80 ?m.

Abstract: An antenna device and a method for configuring the same are provided. The antenna device includes a grounding metal, a grounding part, a radiating part, a feeding part, a proximity sensor, and a sensing metal. The radiating part is electrically connected to the grounding metal through the grounding part. The feeding part is coupled to the grounding metal through a feeding point. The sensing metal is electrically connected to the proximity sensor. The sensing metal is separated from the radiating part at a distance. The distance is less than or equal to one thousandth of a wavelength corresponding to an operating frequency of the antenna device.

Abstract: The present disclosure relates to a rice PAL1 gene, an encoding protein and use thereof. The rice PAL1 gene has the nucleotide sequence shown in SEQ ID NO. 1, and the rice PAL1 protein has the amino acid sequence shown in SEQ ID NO. 4. Mutation of the gene leads to reduction of rice plant height and panicle length, while decreasing the number of primary branches, secondary branches and grains per panicle. It is found that the PAL1 gene can restore a mutant panicle type to a normal phenotype. The present disclosure provides a PAL1 gene functioning as a regulator of the rice panicle length and an encoding protein thereof. A rice panicle type is an important trait influencing rice yield. Therefore, it will be desired to directionally design a plant type and improve the rice yield by regulating panicle traits of rice with the PAL1 gene.

Abstract: In some implementations, a control device may determine a spacing measurement in a first dimension between a wafer on a susceptor and a pre-heat ring of a semiconductor processing tool and/or a gapping measurement in a second dimension between the wafer and the pre-heat ring, using one or more images captured in situ during a process by at least one optical sensor. Accordingly, the control device may generate a command based on a setting associated with the process being performed by the semiconductor processing tool and the spacing measurement and/or the gapping measurement. The control device may provide the command to at least one motor to move the susceptor.

Abstract: A method is provided and includes acquiring a digital slide comprising objects of at least two sizes, the objects including a first object of a first size and a second object of a second size different from the first size, for each of the first object and the second object, acquiring images of a corresponding object in at least two scales based on the digital slide, where the acquired images of the corresponding object in the at least two scales include an image of a larger scale and an image of a smaller scale, the image of the larger scale having a smaller image size and a higher image resolution than the image of the smaller scale, and determining, from the images of the corresponding object in the at least two scales, an image having an image size that corresponds to a size of the corresponding object.

Abstract: The present disclosure relates to a rice PAL1 gene, an encoding protein and use thereof. The rice PAL1 gene has the nucleotide sequence shown in SEQ ID NO. 1, and the rice PAL1 protein has the amino acid sequence shown in SEQ ID NO. 4. Mutation of the gene leads to reduction of rice plant height and panicle length, while decreasing the number of primary branches, secondary branches and grains per panicle. It is found that the PAL1 gene can restore a mutant panicle type to a normal phenotype. The present disclosure provides a PAL1 gene functioning as a regulator of the rice panicle length and an encoding protein thereof. A rice panicle type is an important trait influencing rice yield. Therefore, it will be desired to directionally design a plant type and improve the rice yield by regulating panicle traits of rice with the PAL1 gene.

Abstract: An electrical connector includes an insulating seat and at least one conductive terminal provided therein. The insulating seat includes a rear wall and two side walls, surroundingly forming a mating space. Each side wall includes an extending arm and an elastic arm. The elastic arm has a first arm extending forward from the extending arm and a second arm bending reversely from the first arm and extending backward. The second arm is connected to the rear wall. An opening slot is formed between the first arm and the extending arm and runs forward therethrough. A through slot is formed between the second arm and the first arm. A buckling portion is formed at a side of the second arm away from the first arm to correspond to the through slot and the opening slot in a left-right direction. The conductive terminal has a contact portion exposed to the mating space.

Abstract: An electrical connector includes an insulating seat and at least one conductive terminal provided therein. The insulating seat includes a rear wall and two side walls, surroundingly forming a mating space. Each side wall includes an extending arm and an elastic arm. The elastic arm has a first arm extending forward from the extending arm and a second arm bending reversely from the first arm and extending backward. The second arm is connected to the rear wall. An opening slot is formed between the first arm and the extending arm and runs forward therethrough. A through slot is formed between the second arm and the first arm. A buckling portion is formed at a side of the second arm away from the first arm to correspond to the through slot and the opening slot in a left-right direction. The conductive terminal has a contact portion exposed to the mating space.

Abstract: The present disclosure provides a method for forming a semiconductor device, including: providing a substrate; forming a gate material layer over the substrate; performing a first etching process on the gate material layer to remove a first portion of the gate material layer and expose a first portion of the substrate; performing a first ion implantation process on the first portion of the substrate to form a body region in the substrate, the body region being doped with first dopant ions and extending to under a remaining portion of the gate material layer; and forming a gate electrode by performing a second etching process on the remaining portion of the gate material layer to remove a second portion of the gate material layer, the second portion of the gate material layer being located on a side away from the body region.

Abstract: The present disclosure provides a method for forming a semiconductor device, including: providing a substrate; forming a gate material layer over the substrate; performing a first etching process on the gate material layer to remove a first portion of the gate material layer and expose a first portion of the substrate; performing a first ion implantation process on the first portion of the substrate to form a body region in the substrate, the body region being doped with first dopant ions and extending to under a remaining portion of the gate material layer; and forming a gate electrode by performing a second etching process on the remaining portion of the gate material layer to remove a second portion of the gate material layer, the second portion of the gate material layer being located on a side away from the body region.

Abstract: The present invention provides a pattern verifying method. First, a target pattern is decomposed into a first pattern and a second pattern. A first OPC process is performed for the first pattern to form a first revised pattern, and a second OPC process is performed for the second pattern to form a second revised pattern. An inspection process is performed, wherein the inspection process comprises an after mask inspection (AMI) process, which comprises considering the target pattern, the first pattern and the second pattern.

Abstract: A method for optimizing an integrated circuit layout design includes the following steps. A first integrated circuit layout design including a metal line feature having several metal lines and a second integrated circuit layout design including a hole feature having several holes are obtained. A line-end hole feature of the hole feature is selected by piecing the metal line feature with the hole feature. The line-end hole feature is classified into a single hole feature and a redundant hole feature by spacings between the adjacent holes by a computer system.

Abstract: A method for optimizing an integrated circuit layout design includes the following steps. A first integrated circuit layout design including a metal line feature having several metal lines and a second integrated circuit layout design including a hole feature having several holes are obtained. A line-end hole feature of the hole feature is selected by piecing the metal line feature with the hole feature. The line-end hole feature is classified into a single hole feature and a redundant hole feature by spacings between the adjacent holes by a computer system.

Abstract: The present invention provides a pattern verifying method. First, a target pattern is decomposed into a first pattern and a second pattern. A first OPC process is performed for the first pattern to form a first revised pattern, and a second OPC process is performed for the second pattern to form a second revised pattern. An inspection process is performed, wherein the inspection process comprises an after mask inspection (AMI) process, which comprises considering the target pattern, the first pattern and the second pattern.

Abstract: A control method utilizing a PID controller includes detecting the position of an object and obtaining the position deviation by comparison with a predetermined position value, detecting the vibration of the object and obtaining a vibration value, adjusting the control parameters of the PID controller by analyzing the position deviation, the vibration value, and a predetermined performance of the PID controller, and the PID controller responding to the adjusted control parameters.

Abstract: A control method utilizing a PID controller includes detecting the position of an object and obtaining the position deviation by comparison with a predetermined position value, detecting the vibration of the object and obtaining a vibration value, adjusting the control parameters of the PID controller by analyzing the position deviation, the vibration value, and a predetermined performance of the PID controller, and the PID controller responding to the adjusted control parameters.

Abstract: A liquid crystal display with defect reparability including two vertical common lines and a plurality of horizontal common lines in a pixel, wherein the vertical common lines are parallel to a data line, and each horizontal common line is intersected to connect with each vertical common line. Each horizontal common line is extended to pass through but not touch the data line and connect with a horizontal common line in a neighboring pixel, and the horizontal common lines have overlaps with the data line in a different plane.

Abstract: The present invention comprises a system and method for secure session management and authentication between web sites and web clients. The method includes both secure and non-secure communication protocols, means for switching between secure and non-secure communication protocols, a session cookie and an authcode cookie. The session cookie is used for session management and the authcode cookie is used for authentication. The session cookie is transmitted using a non-secure communication protocol when the web client accesses a non-secure web page, whereas, the authcode cookie is transmitted using a secure communication protocol when the web client accesses a secure web page. Session management architecture and usage of two distinct cookies along with both secure and non-secure communication protocols prevents unauthorized users from accessing sensitive web client or web site information.

Abstract: A liquid crystal display with defect reparability including two vertical common lines and a plurality of horizontal common lines in a pixel, wherein the vertical common lines are parallel to a data line, and each horizontal common line is intersected to connect with each vertical common line. Each horizontal common line is extended to pass through but not touch the data line and connect with a horizontal common line in a neighboring pixel, and the horizontal common lines have overlaps with the data line in a different plane.

Abstract: The present invention comprises a system and method for secure session management and authentication between web sites and web clients. The method includes both secure and non-secure communication protocols, means for switching between secure and non-secure communication protocols, a session cookie and an authcode cookie. The session cookie is used for session management and the authcode cookie is used for authentication. The session cookie is transmitted using a non-secure communication protocol when the web client accesses a non-secure web page, whereas, the authcode cookie is transmitted using a secure communication protocol when the web client accesses a secure web page. Session management architecture and usage of two distinct cookies along with both secure and non-secure communication protocols prevents unauthorized users from accessing sensitive web client or web site information.