Patents by Inventor Yan-Fei Liu

Yan-Fei Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10637363
    Abstract: A converter includes a half-bridge circuit including first and second transistors that are connected in series, the half-bridge circuit is connected in parallel with a voltage input and includes a node connected to both the first and second transistors; a resonant inductor connected to the half-bridge circuit and the primary winding of a transformer; a resonant capacitor connected to the half-bridge circuit and the primary winding; a third transistor with a first terminal connected to the half-bridge circuit and a second terminal directly connected to a first terminal of the resonant inductor; and a rectification stage that is connected to the secondary winding of the transformer and that includes first and second synchronous rectifiers. The rectification stage does not use discrete diodes to provide rectification, and during voltage boost operation, the third transistor is turned on and off to maintain an output voltage level.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: April 28, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hongliang Wang, Yang Chen, Yan-Fei Liu, Jahangir Afsharian, Zhihua Yang, Bing Gong
  • Patent number: 10630197
    Abstract: A power converter circuit includes a rectifier circuit having first and second input terminals that receive an AC input voltage and first and second output terminals that output a DC bus voltage, and a series circuit comprising a switch connected in series with an input capacitor connected across the first and second output terminals. A controller controls the switch so that the switch is on at least during a period when a magnitude of the AC input voltage is less than a selected DC bus voltage, and the switch is off during a period when the magnitude of the AC input voltage is greater than the selected DC bus voltage and less than a peak value of the AC input voltage. Power adapters incorporating these features benefit from low component count, reduced component current stress, reduced size and weight, and low cost, making then suitable for a range of portable devices such as laptop computers and cellphones.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: April 21, 2020
    Assignee: Queen's University at Kingston
    Inventors: Yang Chen, Yan-Fei Liu
  • Publication number: 20200112244
    Abstract: An LLC converter includes a transformer that includes a primary winding and a secondary winding, a resonant stage that includes the primary winding, a switching stage that includes switches and that is connected to an input voltage and the resonant stage, a rectifying stage that is connected to the secondary winding and that provides an output voltage, and a controller that senses the output voltage and that controls switching of the switches based on proportional-integral control of the output voltage to reduce errors in the output voltage with respect to a DC voltage and based on quasi-resonant control of the output voltage to reduce errors in the output voltage with respect to a range of voltages with a frequency bandwidth.
    Type: Application
    Filed: January 26, 2018
    Publication date: April 9, 2020
    Inventors: Yang CHEN, Hongliang WANG, Yan-Fei LIU, Jahangir AFSHARIAN, Bing GONG
  • Patent number: 10615094
    Abstract: Described herein are semiconductor devices and structures with improved power handling and heat dissipation. Embodiments are suitable for implementation in gallium nitride. Devices may be provided as individual square or diamond-shaped dies having electrode terminals at the die corners, tapered electrode bases, and interdigitated electrode fingers. Device matrix structures include a plurality of device dies arranged on a substrate in a matrix configuration with interdigitated conductors. Device lattice structures are based on a unit cell comprising a plurality of individual devices, the unit cells disposed on a chip with geometric periodicity. Also described herein are methods for implementing the semiconductor devices and structures.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: April 7, 2020
    Inventors: Zhanming Li, Yue Fu, Wai Tung Ng, Yan-Fei Liu
  • Publication number: 20200099302
    Abstract: A multi-stage, multi-level DC-DC step-down converter includes a first stage and a second stage having two identical cells connected in parallel. The first stage includes an input capacitor, four switches, and one flying capacitor. The two cells of the second stage each include four switches and one flying capacitor, and an output filter. The cells of the second stage are driven at half the switching frequency of the input stage, and provides a step-down ratio of 4:1. A third stage having four cells may be added to achieve a step-down ratio of 8:1, a fourth stage having eight cells may be added to achieve a step-down ration of 16:1, etc., each additional stage including a doubling of the number of cells connected in parallel, with all cells being substantially identical, and each stage operating at a further reduced fraction of the switching frequency. Embodiments are particularly suitable for applications such as a 48V intermediate bus architecture for servers and datacenters.
    Type: Application
    Filed: September 20, 2019
    Publication date: March 26, 2020
    Inventors: Samuel Dylan Webb, Yan-Fei Liu
  • Patent number: 10586749
    Abstract: Described herein are semiconductor devices and structures with improved power handling and heat dissipation. Embodiments are suitable for implementation in gallium nitride. Devices may be provided as individual square or diamond-shaped dies having electrode terminals at the die corners, tapered electrode bases, and interdigitated electrode fingers. Device matrix structures include a plurality of device dies arranged on a substrate in a matrix configuration with interdigitated conductors. Device lattice structures are based on a unit cell comprising a plurality of individual devices, the unit cells disposed on a chip with geometric periodicity. Also described herein are methods for implementing the semiconductor devices and structures.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: March 10, 2020
    Inventors: Zhanming Li, Yue Fu, Wai Tung Ng, Yan-Fei Liu
  • Publication number: 20200007037
    Abstract: A power regulator includes an input capacitor connected between a first voltage bus and an intermediate point, an output capacitor connected between a second voltage bus and the intermediate point, a plurality of switches and an inductor connected between the input capacitor and the output capacitor, wherein a source of one switch of the plurality of switches is connected to the intermediate point and a protection device connected between the intermediate point and a third voltage bus.
    Type: Application
    Filed: September 9, 2019
    Publication date: January 2, 2020
    Inventors: Hengchun Mao, Yan-Fei Liu, Renhua Wu
  • Publication number: 20200007091
    Abstract: Voltage stabilizing and voltage regulating circuits implemented in GaN HEMT technology provide stable output voltages suitable for use in applications such as GaN power transistor gate drivers and low voltage auxiliary power supplies for GaN integrated circuits. Gate driver and voltage regulator modules include at least one GaN D-mode HEMT (DHEMT) and at least two GaN E-mode HEMTs (EHEMTs) connected together in series, so that the at least one DHEMT operates as a variable resistor and the at least two EHEMTs operate as a Zener diode that limits the output voltage. The gate driver and voltage regulator modules may be implemented as a GaN integrated circuits, and may be monolithically integrated together with other components such as amplifiers and power HEMTs on a single die to provide a GaN HEMT power module IC.
    Type: Application
    Filed: June 22, 2019
    Publication date: January 2, 2020
    Inventors: Zhanming Li, Yue Fu, Yan-Fei Liu
  • Publication number: 20200007119
    Abstract: Voltage stabilizing and voltage regulating circuits implemented in GaN HEMT technology provide stable output voltages suitable for use in applications such as GaN power transistor gate drivers and low voltage auxiliary power supplies for GaN integrated circuits. Gate driver and voltage regulator modules include at least one GaN D-mode HEMT (DHEMT) and at least two GaN E-mode HEMTs (EHEMTs) connected together in series, so that the at least one DHEMT operates as a variable resistor and the at least two EHEMTs operate as a Zener diode that limits the output voltage. The gate driver and voltage regulator modules may be implemented as a GaN integrated circuits, and may be monolithically integrated together with other components such as amplifiers and power HEMTs on a single die to provide a GaN HEMT power module IC.
    Type: Application
    Filed: June 27, 2019
    Publication date: January 2, 2020
    Inventors: Zhanming Li, Yue Fu, Yan-Fei Liu
  • Publication number: 20190379374
    Abstract: A gate driver circuit for a gallium nitride (GaN) power transistor includes a RS-flipflop that receives a first pulse train at an S input terminal and a second pulse train at an R input terminal, and produces an output pulse train, and an amplifier that amplifies the output pulse train and produces a gate driver signal for the GaN power transistor. The RS-flipflop and the amplifier may be implemented together on a GaN monolithic integrated circuit, optionally together with the GaN power transistor. The GaN power transistor may be a high-side switch of a half-bridge circuit. The RS-flipflop may be implemented with enhancement mode and depletion mode GaN high electron mobility transistors (HEMTs). Embodiments avoid drawbacks of prior hybrid (e.g., silicon-GaN) approaches, such as parasitic inductances from bonding wires and on-board metal traces, especially at high operating frequencies, as well as reduce implementation cost and improve performance.
    Type: Application
    Filed: May 27, 2019
    Publication date: December 12, 2019
    Inventors: Zhanming Li, Yan-Fei Liu, Yue Fu, Wai Tung Ng
  • Publication number: 20190378822
    Abstract: Use of gallium nitride (GaN) semiconductor material for power devices is challenging due to low yield caused by high defect density on the wafer. Device layout on the wafer, chip probing, and device packaging increase the yield of large area power devices. Device dies containing a plurality of lower-power sub-devices are used to achieve high power ratings, by connecting only functional sub-devices together in the package, while being tolerant of defective sub-devices by selectively excluding the defective sub-devices. The packages and methods are particularly relevant to GaN power switching devices such as high electron mobility transistors (GaN HEMT).
    Type: Application
    Filed: May 11, 2019
    Publication date: December 12, 2019
    Inventors: Zhanming Li, Guanhou Luo, Yue Fu, Wai Tung Ng, Yan-Fei Liu
  • Patent number: 10498236
    Abstract: Disclosed are multilevel buck converters, and controllers and methods for operating such converters. Embodiments improve the voltage gain (Vo/Vin) of multi-level DC-DC converters, such as three-level converters, that is imposed by a duty cycle limitation in conventional approaches. According to certain embodiments, the duty cycle of switches is controlled to so that the converter output voltage is increased.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: December 3, 2019
    Inventors: Tianshu Liu, Yan-Fei Liu
  • Patent number: 10491123
    Abstract: An LLC resonant converter includes a first phase with a first primary circuit and a second phase with a second primary circuit. The first primary circuit includes a first shared inductor, and the second primary circuit includes a second shared inductor. The first and second shared inductors are connected in parallel with each other. The first and second primary circuits do not include a capacitor that is connected in parallel with each other.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: November 26, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hongliang Wang, Yang Chen, Yan-Fei Liu, Jahangir Afsharian, Zhihua Yang, Bing Gong
  • Patent number: 10476397
    Abstract: Provided are methods and circuits for a resonant converter comprising at least one switch-controlled capacitor, wherein the at least one switch-controlled capacitor controls a resonant frequency of the resonant tank circuit. Provided are constant and variable switching frequency embodiments, and fill-wave and half-wave switch-controlled capacitor embodiments. Also provided are interleaved resonant converters based on constant and variable switching frequency, and full-wave and half-wave switch-controlled capacitor resonant converter embodiments. Interleaved embodiments overcome load sharing problems associated with prior interleaved resonant converters and enable phase shedding to improve light load efficiency.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: November 12, 2019
    Assignee: Ganpower International Inc.
    Inventors: Yan-Fei Liu, Zhiyuan Hu
  • Patent number: 10468965
    Abstract: Disclosed are multi-stage multilevel DC-DC step-down converters. Stages may include three or four switches, and switches of each stage are operated at selected duty cycles such that each stage reduces an input voltage by one-half and voltage stress on switches is reduced. In some embodiments only a single output inductor is used in an LC filter, and the inductor may be very small as compared with a conventional Buck converter. Thus, embodiments provide DC-DC step-down converters with high power density and efficiency.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: November 5, 2019
    Assignee: Queen's University at Kingston
    Inventors: Tianshu Liu, Yan-Fei Liu
  • Patent number: 10447173
    Abstract: A single-phase five-level active clamping converter unit and a converter. The single-phase five-level active clamping converter unit has three input ends and one output end, and also comprises: a suspension capacitor and a topological control portion. The topological control portion is connected to the suspension capacitor and the three input ends and one output end of the single-phase five-level active clamping converter unit, is connected to a plurality of control ends, and is suitable for the supply of at least eight operating modes under the control of a control signal accessing the control ends. In the single-phase five-level active clamping converter unit, a topological structure is easy to design, and is simple and convenient to control.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: October 15, 2019
    Inventors: Hongliang Wang, Yan-Fei Liu
  • Patent number: 10411596
    Abstract: A power regulator comprises a first power switch configured to carry a pulsed current, an input capacitor between a positive terminal of an input voltage bus and a return point, an output capacitor between a positive terminal of an output voltage bus and the return point and a protection device coupled between the return point and a common return point of the input voltage bus and the output voltage bus, wherein the pulsed current is configured to flow through the protection device.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: September 10, 2019
    Assignee: Futurewei Technologies, Inc.
    Inventors: Hengchun Mao, Yan-Fei Liu, Renhua Wu
  • Publication number: 20190260303
    Abstract: A power converter circuit includes a rectifier circuit having first and second input terminals that receive an AC input voltage and first and second output terminals that output a DC bus voltage, and a series circuit comprising a switch connected in series with an input capacitor connected across the first and second output terminals. A controller controls the switch so that the switch is on at least during a period when a magnitude of the AC input voltage is less than a selected DC bus voltage, and the switch is off during a period when the magnitude of the AC input voltage is greater than the selected DC bus voltage and less than a peak value of the AC input voltage. Power adapters incorporating these features benefit from low component count, reduced component current stress, reduced size and weight, and low cost, making then suitable for a range of portable devices such as laptop computers and cellphones.
    Type: Application
    Filed: February 20, 2019
    Publication date: August 22, 2019
    Inventors: Yang Chen, Yan-Fei Liu
  • Patent number: 10389271
    Abstract: A single-phase four-level inverter circuit topology and a three-phase four-level inverter circuit topology. The single-phase four-level inverter circuit topology is adapted to be used with two series-connected direct current power sources, so as to enable a first direct current power source or a second direct current power source to supply power to a load of the four-level inverter circuit topology, alternatively, any one of two direct current power sources is first algebraically superimposed with a flying capacitor and then supplies the power to the load of the four-level inverter circuit topology (M), thereby making the four-level inverter circuit topology output four different levels.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: August 20, 2019
    Inventors: Hongliang Wang, Yan-Fei Liu
  • Patent number: 10388743
    Abstract: This invention relates to interdigitated electrodes for power electronic and optoelectronic devices where field and current distribution determine the device performance. Described are geometries based on rounded asymmetrical fingers and electrode bases of varying width. Simulations demonstrate benefits for reducing self-heating and thermal power loss, which reduces overall on-state resistance and increases reverse break down voltages.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: August 20, 2019
    Inventors: Zhanming Li, Yue Fu, Wai Tung Ng, Yan-Fei Liu