Abstract: An external cache management unit for use with a 3D-RAM frame buffer and suitable for use in a computer graphics system is described. The unit may reduce power consumption within the 3D-RAM by performing partial block write-back according to status information stored in an array of dirty tag bits. Periodic level one cache block cleansing is provided for during empty memory cycles.

Abstract: The refrigeration system of the present invention includes multiple economizer circuits. After flowing through the condenser, a first path of refrigerant is split from the main path. The refrigerant in the first path is expanded to a lower pressure and cools the refrigerant in the main path in the high pressure economizer heat exchanger. The refrigerant in the first path then returns to the compressor in a high pressure economizer port. A second path of refrigerant is then split from the main path. The refrigerant in the second flow path is expanded to a lower pressure and cools the refrigerant in the main path in the low pressure economizer heat exchanger. The refrigerant in the second path then return to the compressor in a low pressure economizer port. The refrigerant in the main path is then evaporated. The dual stage economizer refrigeration system can be employed with a screw compressor or a scroll compressor.

Abstract: The refrigeration system of the present invention includes multiple economizer circuits. After flowing through the condenser, a first path of refrigerant is split from the main path. The refrigerant in the first path is expanded to a lower pressure and cools the refrigerant in the main path in the high pressure economizer heat exchanger. The refrigerant in the first path then returns to the compressor in a high pressure economizer port. A second path of refrigerant is then split from the main path. The refrigerant in the second flow path is expanded to a lower pressure and cools the refrigerant in the main path in the low pressure economizer heat exchanger. The refrigerant in the second path then return to the compressor in a low pressure economizer port. The refrigerant in the main path is then evaporated. The dual stage economizer refrigeration system can be employed with a screw compressor or a scroll compressor.

Abstract: A scroll expresser of a refrigerant system includes a non-orbiting expander scroll plate and an orbiting expander scroll plate which form a plurality of expansion chambers and a non-orbiting compressor scroll plate and a orbiting compressor scroll plate which form a plurality of compression chambers. The scroll expresser expands high pressure refrigerant in the expansion chambers to low pressure vapor refrigerant and liquid refrigerant. The liquid refrigerant exits the scroll expresser for evaporation. The vapor refrigerant is compressed in the compression chambers and mixes with the refrigerant exiting the compressor. Alternatively, the orbiting scroll plates are integrated into one component.

Abstract: The expansion device in a refrigeration or air conditioning system is an expressor. The expresser is made up of a twin screw expander and a twin screw compressor with rotors of the expander functioning as timing gears.

Abstract: A graphics system may include a frame buffer, a processing device coupled to access data in the frame buffer, a frame buffer interface coupled to the frame buffer, and an output controller configured to assert a request for display data to provide to a display device. The frame buffer interface may receive the request for display data from the output controller and delay providing the request for display data to the frame buffer if the processing device is currently requesting access to a portion of the frame buffer targeted by the request for display data. For example, if the frame buffer includes several memory banks and the request for display data targets a first bank, the frame buffer interface may delay providing the request for display data to the frame buffer if the processing device is currently requesting access to the first bank.

Abstract: A graphics system may include a frame buffer that includes several sets of one or more memory banks and a cache. The frame buffer may load data from one of the memory banks into the cache in response to receiving a cache fill request. Each set of memory banks is accessible independently of each other set of memory banks. A frame buffer interface coupled to the frame buffer includes a plurality of cache fill request queues. Each cache fill request queue is configured to store one or more cache fill requests targeting a corresponding one of the sets of memory banks. The frame buffer interface is configured to select a cache fill request from one of the cache fill request queues that stores cache fill requests targeting a set of memory banks that is not currently being accessed and to provide the selected cache fill request to the frame buffer.

Abstract: A system for managing the control of a bi-directional data bus between a master unit and a slave unit. The master couples to the slave through a request opcode bus, a reply opcode bus and the data bus. If the master is in a bus driving state (with respect to the data bus) and receives a read request, the master relinquishes bus control and sends a read request through the request opcode bus. The slave unit assumes bus control and sends the requested data through the data bus. If the master is in a bus sensing state and receives a write request, the master sends a last read opcode to the slave via the request opcode bus, and waits for the slave to return a special token through the reply opcode bus. Upon receiving the special token the master unit assumes bus control and performs the write transaction.

Abstract: An external cache management unit for use with 3D-RAM and suitable for use in a computer graphics system is described. The unit maintains and tracks the status of level one cache memory in the 3D-RAM. The unit identifies dirty blocks of cache memory and prioritizes block cleansing based on a least used algorithm. Periodic block cleansing during empty memory cycles is provided for, and may also be prompted on demand.

Abstract: A system and method for generating pixels for a display device. The system may include a sample buffer for storing a plurality samples in a memory, a sample cache for caching recently accessed samples, and a sample filter unit for filtering one or more samples to generate a pixel. The generated pixels may then be stored in a frame buffer or provided to a display device. The method operates to take advantage of the common samples shared by neighboring pixels in both the x and y directions for reduced sample buffer accesses and improved performance. The method involves reading samples from the memory that correspond to pixels in a plurality of neighboring scan lines, and possibly also to multiple pixels in each of these scan lines. The samples may be stored in a cache memory and then accessed from the cache memory for filtering. The method maximizes use of the common samples shared by neighboring pixels in both the x and y directions.

Abstract: A scroll expresser of a refrigerant system includes a non-orbiting expander scroll plate and an orbiting expander scroll plate which form a plurality of expansion chambers and a non-orbiting compressor scroll plate and a orbiting compressor scroll plate which form a plurality of compression chambers. The scroll expresser expands high pressure refrigerant in the expansion chambers to low pressure vapor refrigerant and liquid refrigerant. The liquid refrigerant exits the scroll expresser for evaporation. The vapor refrigerant is compressed in the compression chambers and mixes with the refrigerant exiting the compressor. Alternatively, the orbiting scroll plates are integrated into one component.

Abstract: Saturated or sub-cooled liquid is supplied to the expander of an expressor. Starting just prior to the end of the inlet process or just after the completion of the inlet process, high pressure vapor from the expressor compressor discharge is supplied to the cavity defining a trapped volume under going expansion.

Abstract: A graphics system includes a frame buffer, a write address generator, and a pixel buffer. A burst of pixels received from the frame buffer may not be in display order. In one embodiment, a write address generator calculates a write address for each pixel in the burst of pixels output from the frame buffer. The write address corresponds to a relative display order within the burst for each respective pixel. Each pixel in the burst is stored to its write address in the pixel buffer. This way, the pixels in the burst are stored in display order within the pixel buffer.

Abstract: The invention provides improved processes for oligonucleotide synthesis utilizing arenes as solvents for detritylation of oligonucleotides.

Abstract: A system and method for packing pixels together to provide a increased fill rate in a frame buffer hardware in the graphics system. The graphics system may be configured to receive and rasterize graphics data at a faster cycle rate than the system's frame buffer memory fill rate. The output from the rasterization hardware may be stored in a FIFO memory that is configured to selectively shift pixels in order to improve fill rate performance. The FIFO memory may be configured to ensure that the pixels meet certain criteria in order to prevent page faults and interleave conflicts that could reduce the fill rate. The FIFO memory may also be configured to remove empty cycles that occur as a result of the pixel packing.

Abstract: The invention relates to the chemical synthesis of oligonucleotides and to chemical entities useful in such synthesis. More particularly, the invention relates to sulfurization of the internucleotide linkages of oligonucleotides. The invention provides a process to synthesize new sulfur transfer reagents and a process for their use in sulfurizing oligonucleotides. The sulfur transfer reagents according to the invention are inexpensive to make, stable in storage and in solution, and highly efficient in sulfurization.

Abstract: An external cache management unit for use with a 3D-RAM frame buffer and suitable for use in a computer graphics system is described. The unit may reduce power consumption within the 3D-RAM by performing partial block write-back according to status information stored in an array of dirty tag bits. Periodic level one cache block cleansing is provided for during empty memory cycles.

Abstract: A system and method for rasterizing and rendering graphics data is disclosed. Vertices may be grouped to form primitives such as triangles, which are rasterized using two-dimensional arrays of samples bins. Individual samples may be selected from the bins according to different criteria such as memory bank allocation to improve utilization of the system's rendering pipeline. Since the arrays may have more bins than the number of evaluation units in the rendering pipeline, the samples from the bins may be stored to FIFO memories to allow invalid or empty samples (those outside the primitive being rendered) to be removed. The samples may then be filtered to form pixels that are displayable to form an image on a display device.

Abstract: An external cache management unit for use with a 3D-RAM frame buffer and suitable for use in a computer graphics system is described. The unit may reduce power consumption within the 3D-RAM by performing partial block write-back according to status information stored in an array of dirty tag bits. Periodic level one cache block cleansing is provided for during empty memory cycles.

Abstract: The invention provides passivated organic polymer supports, processes for their preparation and processes for their use in oligonucleotide synthesis that allow for highly efficient solid phase synthesis of oligonucleotides.