Patents by Inventor Yan Wen CHUNG

Yan Wen CHUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11791293
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes an antenna zone and a routing zone. The routing zone is disposed on the antenna zone, where the antenna zone includes a first insulation layer and two or more second insulation layer and a thickness of the first insulation layer is different from that of the second insulation layer.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: October 17, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Yan Wen Chung, Wei Chu Sun
  • Patent number: 11329007
    Abstract: A wiring structure includes a conductive structure, a surface structure and at least one through via. The conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The surface structure is disposed adjacent to a top surface of the conductive structure. The through via extends through the surface structure and extending into at least a portion of the conductive structure.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: May 10, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Yan Wen Chung, Huei-Shyong Cho
  • Publication number: 20220005771
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes an antenna zone and a routing zone. The routing zone is disposed on the antenna zone, where the antenna zone includes a first insulation layer and two or more second insulation layer and a thickness of the first insulation layer is different from that of the second insulation layer.
    Type: Application
    Filed: September 20, 2021
    Publication date: January 6, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Hung HUANG, Yan Wen CHUNG, Wei Chu SUN
  • Patent number: 11211325
    Abstract: A semiconductor package may include a first substrate and a second substrate, a redistribution layer (RDL), a first conductive via and a second conductive via. The first substrate has a first surface and a second surface opposite to the first surface. The second substrate has a first surface and a second surface opposite to the first surface. The RDL is disposed on the first surface of the first substrate and the first surface of the second substrate. The first conductive via passes through the RDL and is electrically connected to the first substrate. The second conductive via passes through the RDL and is electrically connected to the second substrate.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: December 28, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Yan Wen Chung, Min Lung Huang
  • Patent number: 11127697
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes an antenna zone and a routing zone. The routing zone is disposed on the antenna zone, where the antenna zone includes a first insulation layer and two or more second insulation layer and a thickness of the first insulation layer is different from that of the second insulation layer.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: September 21, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Yan Wen Chung, Wei Chu Sun
  • Patent number: 11031326
    Abstract: A wiring structure includes an insulating layer and a conductive structure. The insulating layer has an upper surface and a lower surface opposite to the upper surface, and defines an opening extending through the insulating layer. The conductive structure is disposed in the opening of the insulating layer, and includes a first barrier layer and a wetting layer. The first barrier layer is disposed on a sidewall of the opening of the insulating layer, and defines a through hole extending through the first barrier layer. The wetting layer is disposed on the first barrier layer. A portion of the wetting layer is exposed from the through hole of the first barrier layer and the lower surface of the insulating layer to form a ball pad.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: June 8, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Chien-Mei Huang, Yan Wen Chung
  • Publication number: 20210159168
    Abstract: A semiconductor package may include a first substrate and a second substrate, a redistribution layer (RDL), a first conductive via and a second conductive via. The first substrate has a first surface and a second surface opposite to the first surface. The second substrate has a first surface and a second surface opposite to the first surface. The RDL is disposed on the first surface of the first substrate and the first surface of the second substrate. The first conductive via passes through the RDL and is electrically connected to the first substrate. The second conductive via passes through the RDL and is electrically connected to the second substrate.
    Type: Application
    Filed: November 26, 2019
    Publication date: May 27, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Hung HUANG, Yan Wen CHUNG, Min Lung HUANG
  • Publication number: 20210013163
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes an antenna zone and a routing zone. The routing zone is disposed on the antenna zone, where the antenna zone includes a first insulation layer and two or more second insulation layer and a thickness of the first insulation layer is different from that of the second insulation layer.
    Type: Application
    Filed: July 10, 2019
    Publication date: January 14, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Hung HUANG, Yan Wen CHUNG, Wei Chu SUN
  • Patent number: 10892213
    Abstract: A wiring structure includes an upper conductive structure, a lower conductive structure, an adhesion layer and at least one outer via. The upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The adhesion layer is interposed between the upper conductive structure and the lower conductive structure to bond the upper conductive structure and the lower conductive structure together. The outer via extends through at least a portion of the upper conductive structure and the adhesion layer, and electrically connected to the circuit layer of the lower conductive structure.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: January 12, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Li-Yu Hsieh, Yan Wen Chung
  • Publication number: 20200381369
    Abstract: A wiring structure includes a conductive structure, a surface structure and at least one through via. The conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The surface structure is disposed adjacent to a top surface of the conductive structure. The through via extends through the surface structure and extending into at least a portion of the conductive structure.
    Type: Application
    Filed: August 18, 2020
    Publication date: December 3, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Hung HUANG, Yan Wen CHUNG, Huei-Shyong CHO
  • Patent number: 10790241
    Abstract: A wiring structure includes a conductive structure, a surface structure and at least one through via. The conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The surface structure is disposed adjacent to a top surface of the conductive structure. The through via extends through the surface structure and extending into at least a portion of the conductive structure.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: September 29, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Yan Wen Chung, Huei-Shyong Cho
  • Publication number: 20200279815
    Abstract: A wiring structure includes a conductive structure, a surface structure and at least one through via. The conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The surface structure is disposed adjacent to a top surface of the conductive structure. The through via extends through the surface structure and extending into at least a portion of the conductive structure.
    Type: Application
    Filed: February 28, 2019
    Publication date: September 3, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Hung HUANG, Yan Wen CHUNG, Huei-Shyong CHO
  • Publication number: 20200273722
    Abstract: A semiconductor package structure includes a first insulating layer, a first conductive layer, a multi-layered circuit structure, a protection layer, and a semiconductor chip electrically connected to the multi-layered circuit structure. The first insulating layer defines a first through hole extending through the first insulating layer. The first conductive layer includes a conductive pad disposed in the first through hole and a trace disposed on an upper surface of the first insulating layer. The multi-layered circuit structure is disposed on an upper surface of the first conductive layer. The multi-layered circuit structure includes a bonding region disposed on the conductive pad of the first conductive layer and an extending region disposed on the trace of the first conductive layer. The protection layer covers the upper surface of the first insulating layer and the extending region of the multi-layered circuit structure, and exposes the bonding region of the multi-layered circuit structure.
    Type: Application
    Filed: May 8, 2020
    Publication date: August 27, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Hung HUANG, Yan Wen CHUNG
  • Publication number: 20200211945
    Abstract: A wiring structure includes an upper conductive structure, a lower conductive structure, an adhesion layer and at least one outer via. The upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The adhesion layer is interposed between the upper conductive structure and the lower conductive structure to bond the upper conductive structure and the lower conductive structure together.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Hung HUANG, Li-Yu HSIEH, Yan Wen CHUNG
  • Publication number: 20200194361
    Abstract: A wiring structure includes an insulating layer and a conductive structure. The insulating layer has an upper surface and a lower surface opposite to the upper surface, and defines an opening extending through the insulating layer. The conductive structure is disposed in the opening of the insulating layer, and includes a first barrier layer and a wetting layer. The first barrier layer is disposed on a sidewall of the opening of the insulating layer, and defines a through hole extending through the first barrier layer. The wetting layer is disposed on the first barrier layer. A portion of the wetting layer is exposed from the through hole of the first barrier layer and the lower surface of the insulating layer to form a ball pad.
    Type: Application
    Filed: February 26, 2020
    Publication date: June 18, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Hung HUANG, Chien-Mei HUANG, Yan Wen CHUNG
  • Patent number: 10651052
    Abstract: A semiconductor package structure includes a first insulating layer, a first conductive layer, a multi-layered circuit structure, a protection layer, and a semiconductor chip electrically connected to the multi-layered circuit structure. The first insulating layer defines a first through hole extending through the first insulating layer. The first conductive layer includes a conductive pad disposed in the first through hole and a trace disposed on an upper surface of the first insulating layer. The multi-layered circuit structure is disposed on an upper surface of the first conductive layer. The multi-layered circuit structure includes a bonding region disposed on the conductive pad of the first conductive layer and an extending region disposed on the trace of the first conductive layer. The protection layer covers the upper surface of the first insulating layer and the extending region of the multi-layered circuit structure, and exposes the bonding region of the multi-layered circuit structure.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: May 12, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Yan Wen Chung
  • Patent number: 10643937
    Abstract: A wiring structure includes an insulating layer and a conductive structure. The insulating layer has an upper surface and a lower surface opposite to the upper surface, and defines an opening extending through the insulating layer. The conductive structure is disposed in the opening of the insulating layer, and includes a first barrier layer and a wetting layer. The first barrier layer is disposed on a sidewall of the opening of the insulating layer, and defines a through hole extending through the first barrier layer. The wetting layer is disposed on the first barrier layer. A portion of the wetting layer is exposed from the through hole of the first barrier layer and the lower surface of the insulating layer to form a ball pad.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: May 5, 2020
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Hung Huang, Chien-Mei Huang, Yan Wen Chung
  • Patent number: 10522492
    Abstract: A wiring structure includes a dielectric layer and a first patterned conductive layer on the dielectric layer. The dielectric layer has a first region and a second region. The first patterned conductive layer includes a number of fine conductive lines and a number of dummy conductive structures. The number of conductive lines include a first number of conductive lines on the first region and a second number of conductive lines on the second region, and the number of dummy conductive structures include a first number of dummy conductive structures on the second region. The first number of conductive lines occupy a first area on the first region, and the second number of conductive lines and the first number of dummy conductive structures occupy a second area on the second region. A ratio of the second area to the first area is greater than or equal to about 80%.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: December 31, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Yan Wen Chung, Chien-Mei Huang
  • Publication number: 20190348352
    Abstract: A wiring structure includes an insulating layer and a conductive structure. The insulating layer has an upper surface and a lower surface opposite to the upper surface, and defines an opening extending through the insulating layer. The conductive structure is disposed in the opening of the insulating layer, and includes a first barrier layer and a wetting layer. The first barrier layer is disposed on a sidewall of the opening of the insulating layer, and defines a through hole extending through the first barrier layer. The wetting layer is disposed on the first barrier layer. A portion of the wetting layer is exposed from the through hole of the first barrier layer and the lower surface of the insulating layer to form a ball pad.
    Type: Application
    Filed: May 8, 2018
    Publication date: November 14, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Hung HUANG, Chien-Mei HUANG, Yan Wen CHUNG
  • Patent number: 10468340
    Abstract: The present disclosure relates to a wiring structure and a semiconductor package. The wiring structure comprises a first wiring pattern, a dielectric layer and a dummy structure. The first wiring pattern includes a conductive land having a width W1 and a surface area A, and a conductive trace having a width W2 and electrically connected to the conductive land, wherein ((W1*W2)/A)*100%? about 25%. The dielectric layer covers the first wiring pattern, and the dummy structure is adjacent to the conductive trace.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: November 5, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Yan Wen Chung, Wei Chu Sun