Patents by Inventor Yan Wen

Yan Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200273722
    Abstract: A semiconductor package structure includes a first insulating layer, a first conductive layer, a multi-layered circuit structure, a protection layer, and a semiconductor chip electrically connected to the multi-layered circuit structure. The first insulating layer defines a first through hole extending through the first insulating layer. The first conductive layer includes a conductive pad disposed in the first through hole and a trace disposed on an upper surface of the first insulating layer. The multi-layered circuit structure is disposed on an upper surface of the first conductive layer. The multi-layered circuit structure includes a bonding region disposed on the conductive pad of the first conductive layer and an extending region disposed on the trace of the first conductive layer. The protection layer covers the upper surface of the first insulating layer and the extending region of the multi-layered circuit structure, and exposes the bonding region of the multi-layered circuit structure.
    Type: Application
    Filed: May 8, 2020
    Publication date: August 27, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Hung HUANG, Yan Wen CHUNG
  • Publication number: 20200212439
    Abstract: The present disclosure provides a negative electrode active material, a battery and a device. The negative electrode active material comprises a first silicon oxide and a second silicon oxide, wherein, a ratio of a particle diameter Dn10 of the first silicon oxide to a particle diameter Dn10 of the second silicon oxide is 8˜25, the particle diameter Dn10 of the first silicon oxide is 1.0 ?m˜5.0 ?m, the particle diameter Dn10 of the second silicon oxide is 0.05 ?m˜0.50 ?m. By selecting two kinds of silicon oxides with specific ranges of Dn10 to match with each other, the present disclosure controls the thickness rebound of negative electrode plate, ensures good electrical contact between the negative electrode active material particles, in turn is beneficial to improve the cycle stability and the cycle-life of the battery.
    Type: Application
    Filed: December 20, 2019
    Publication date: July 2, 2020
    Inventors: Yuqun ZENG, Chengdu Liang, Yuzhen Zhao, Qisen Huang, Yingjie Guan, Yan Wen
  • Publication number: 20200211945
    Abstract: A wiring structure includes an upper conductive structure, a lower conductive structure, an adhesion layer and at least one outer via. The upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The adhesion layer is interposed between the upper conductive structure and the lower conductive structure to bond the upper conductive structure and the lower conductive structure together.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Hung HUANG, Li-Yu HSIEH, Yan Wen CHUNG
  • Publication number: 20200194361
    Abstract: A wiring structure includes an insulating layer and a conductive structure. The insulating layer has an upper surface and a lower surface opposite to the upper surface, and defines an opening extending through the insulating layer. The conductive structure is disposed in the opening of the insulating layer, and includes a first barrier layer and a wetting layer. The first barrier layer is disposed on a sidewall of the opening of the insulating layer, and defines a through hole extending through the first barrier layer. The wetting layer is disposed on the first barrier layer. A portion of the wetting layer is exposed from the through hole of the first barrier layer and the lower surface of the insulating layer to form a ball pad.
    Type: Application
    Filed: February 26, 2020
    Publication date: June 18, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Hung HUANG, Chien-Mei HUANG, Yan Wen CHUNG
  • Patent number: 10651052
    Abstract: A semiconductor package structure includes a first insulating layer, a first conductive layer, a multi-layered circuit structure, a protection layer, and a semiconductor chip electrically connected to the multi-layered circuit structure. The first insulating layer defines a first through hole extending through the first insulating layer. The first conductive layer includes a conductive pad disposed in the first through hole and a trace disposed on an upper surface of the first insulating layer. The multi-layered circuit structure is disposed on an upper surface of the first conductive layer. The multi-layered circuit structure includes a bonding region disposed on the conductive pad of the first conductive layer and an extending region disposed on the trace of the first conductive layer. The protection layer covers the upper surface of the first insulating layer and the extending region of the multi-layered circuit structure, and exposes the bonding region of the multi-layered circuit structure.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: May 12, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Yan Wen Chung
  • Patent number: 10643937
    Abstract: A wiring structure includes an insulating layer and a conductive structure. The insulating layer has an upper surface and a lower surface opposite to the upper surface, and defines an opening extending through the insulating layer. The conductive structure is disposed in the opening of the insulating layer, and includes a first barrier layer and a wetting layer. The first barrier layer is disposed on a sidewall of the opening of the insulating layer, and defines a through hole extending through the first barrier layer. The wetting layer is disposed on the first barrier layer. A portion of the wetting layer is exposed from the through hole of the first barrier layer and the lower surface of the insulating layer to form a ball pad.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: May 5, 2020
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Hung Huang, Chien-Mei Huang, Yan Wen Chung
  • Patent number: 10569273
    Abstract: A method and an apparatus for thermal processing of nucleic acid in a thermal profile. The method employs at least a first bath and a second bath, the method further employing a reactor holder for holding reactor(s) accommodating reaction material containing the nucleic acid. The method includes maintaining bath mediums in the baths at two different temperatures; and alternately allowing the reactor(s) to be in the two baths in a plurality of thermal cycles to alternately attain a predetermined high target temperature THT, and a predetermined low target temperature TLT, wherein the bath medium in at least one of the baths is a high thermal conductivity powder.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: February 25, 2020
    Assignee: STAR ARRAY PTE LTD
    Inventors: Haiqing Gong, Yan Wen, Xudong Zeng
  • Patent number: 10522492
    Abstract: A wiring structure includes a dielectric layer and a first patterned conductive layer on the dielectric layer. The dielectric layer has a first region and a second region. The first patterned conductive layer includes a number of fine conductive lines and a number of dummy conductive structures. The number of conductive lines include a first number of conductive lines on the first region and a second number of conductive lines on the second region, and the number of dummy conductive structures include a first number of dummy conductive structures on the second region. The first number of conductive lines occupy a first area on the first region, and the second number of conductive lines and the first number of dummy conductive structures occupy a second area on the second region. A ratio of the second area to the first area is greater than or equal to about 80%.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: December 31, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Yan Wen Chung, Chien-Mei Huang
  • Patent number: 10496505
    Abstract: The present invention discloses an IC test method including the following steps: generating N test patterns; testing each of M chip(s) according to the N test patterns so as to generate N×M records of quiescent DC current (IDDQ) data; generating N reference values according to the N×M records, in which each of the N reference values is generated according to M record(s) of the N×M records, and the M record(s) and the reference value generated thereupon are related to the same one of the N test patterns; obtaining a reference order of the N test patterns according to the N reference values and a sorting rule; reordering the N×M records by the reference order so as to obtain reordered N×M records; generating an IDDQ range according to the reordered N×M records; and determining whether any of the M chip(s) is defective based on the IDDQ range.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: December 3, 2019
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Wen-Hsuan Hsu, Ying-Yen Chen, Cheng-Yan Wen, Chia-Tso Chao, Jih-Nung Lee
  • Publication number: 20190348352
    Abstract: A wiring structure includes an insulating layer and a conductive structure. The insulating layer has an upper surface and a lower surface opposite to the upper surface, and defines an opening extending through the insulating layer. The conductive structure is disposed in the opening of the insulating layer, and includes a first barrier layer and a wetting layer. The first barrier layer is disposed on a sidewall of the opening of the insulating layer, and defines a through hole extending through the first barrier layer. The wetting layer is disposed on the first barrier layer. A portion of the wetting layer is exposed from the through hole of the first barrier layer and the lower surface of the insulating layer to form a ball pad.
    Type: Application
    Filed: May 8, 2018
    Publication date: November 14, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Hung HUANG, Chien-Mei HUANG, Yan Wen CHUNG
  • Patent number: 10468340
    Abstract: The present disclosure relates to a wiring structure and a semiconductor package. The wiring structure comprises a first wiring pattern, a dielectric layer and a dummy structure. The first wiring pattern includes a conductive land having a width W1 and a surface area A, and a conductive trace having a width W2 and electrically connected to the conductive land, wherein ((W1*W2)/A)*100%? about 25%. The dielectric layer covers the first wiring pattern, and the dummy structure is adjacent to the conductive trace.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: November 5, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Yan Wen Chung, Wei Chu Sun
  • Publication number: 20190255076
    Abstract: The described invention relates to small molecule therapeutic compounds capable of reducing the incidence of intracerebral hemorrhage and brain microhemorrhages identified using zebrafish and mouse models of intracerebral hemorrhage and brain microhemorrhages.
    Type: Application
    Filed: March 11, 2019
    Publication date: August 22, 2019
    Inventors: Xiao-Yan Wen, R. Loch MacDonald, Andrew Baker, Tom A. Schweizer
  • Publication number: 20190221446
    Abstract: A semiconductor package structure includes a first insulating layer, a first conductive layer, a multi-layered circuit structure, a protection layer, and a semiconductor chip electrically connected to the multi-layered circuit structure. The first insulating layer defines a first through hole extending through the first insulating layer. The first conductive layer includes a conductive pad disposed in the first through hole and a trace disposed on an upper surface of the first insulating layer. The multi-layered circuit structure is disposed on an upper surface of the first conductive layer. The multi-layered circuit structure includes a bonding region disposed on the conductive pad of the first conductive layer and an extending region disposed on the trace of the first conductive layer. The protection layer covers the upper surface of the first insulating layer and the extending region of the multi-layered circuit structure, and exposes the bonding region of the multi-layered circuit structure.
    Type: Application
    Filed: January 12, 2018
    Publication date: July 18, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Hung HUANG, Yan Wen CHUNG
  • Patent number: 10292991
    Abstract: The described invention relates to small molecule therapeutic compounds capable of reducing the incidence of intracerebral hemorrhage and brain microhemorrhages identified using zebrafish and mouse models of intracerebral hemorrhage and brain microhemorrhages.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: May 21, 2019
    Assignee: Unity Health Toronto
    Inventors: Xiao-Yan Wen, R. Loch Macdonald, Andrew Baker, Tom A. Schweizer
  • Publication number: 20190136190
    Abstract: The present disclosure describes methods of differentiating cardiomyocyte progenitor cells and mature cardiomyocyte cells from pluripotent stem cells. The methods may include differentiating pluripotent stems cells on a substrate including (i) laminin-511 or 521 and (ii) laminin-221. The cardiomyocyte progenitor cells and mature cardiomyocyte cells produced by the methods may form a human heart muscle cell line for use in regenerative cardiology. Also described are methods of identifying functional cardiomyocyte progenitor cells and their use in therapeutic applications.
    Type: Application
    Filed: June 22, 2018
    Publication date: May 9, 2019
    Inventors: Karl Tryggvason, Yan Wen Yap, Aida Moreno Moral
  • Publication number: 20190134639
    Abstract: An apparatus for thermal processing of nucleic acid in a thermal profile. The apparatus employs a reactor holder for holding reactors to accommodate reaction material containing nucleic acid. The apparatus includes at least two baths separated by thermally insulating partition plate(s) where bath mediums are each maintainable at a predetermined temperature; and a transfer means for allowing the reactors to change position once or plurality of times between any two adjacent baths by selectively opening the partition plate(s) and without lifting the reactors out of the baths.
    Type: Application
    Filed: December 6, 2018
    Publication date: May 9, 2019
    Applicant: STAR ARRAY PTE LTD
    Inventors: Haiqing GONG, Yan WEN, Xudong ZENG
  • Publication number: 20190118184
    Abstract: Apparatus and method for thermal processing of nucleic acid in a thermal profile is provided. The apparatus employs a reactor holder for holding reactor(s) each accommodating reaction material containing the nucleic acid. The apparatus comprises a first bath; and a second bath, bath mediums in the baths being respectively maintainable at two different temperatures THIGH and TLOW; and a transfer means for allowing the reactor(s) to be in the two baths in a plurality of thermal cycles to alternately attain: a predetermined high target temperature THT, and a predetermined low target temperature TLT, while the apparatus adapts to a temperature-offset feature defined by at least one condition from the group consisting: a) the THT is lower than the THIGH, b) the TLT is higher than the TLOW, and c) the conditions at a) and b).
    Type: Application
    Filed: June 9, 2017
    Publication date: April 25, 2019
    Applicant: STAR ARRAY PTE LTD
    Inventors: Haiqing GONG, Yan WEN, Xudong ZENG
  • Publication number: 20190111435
    Abstract: An apparatus for thermally processing reaction material containing nucleic acid is provided. A reaction material is contained in reactors. The apparatus includes a reactor holder for statically holding the reactors; at least two heating means each being maintainable at a user specifiable temperature; and a transport means for positioning the heating means to make a contact with the reactors one at a time for specified duration. The positioning is conductable once or over a plurality of times for thermally processing the reactors between a plurality of temperatures.
    Type: Application
    Filed: December 10, 2018
    Publication date: April 18, 2019
    Applicant: STAR ARRAY PTE LTD
    Inventors: Haiqing GONG, Yan WEN, Xudong ZENG
  • Publication number: 20190105656
    Abstract: An apparatus for thermal processing nucleic acid in a thermal profile. The apparatus employs a reactor holder for holding reactor(s) each accommodating reaction material containing the nucleic acid. The apparatus includes a first bath; and a second bath, bath mediums in the baths being respectively maintainable at two different temperatures; and a transfer means for allowing the reactor(s) to be in the two baths in a plurality of thermal cycles to alternately attain: a predetermined high target temperature THT, and a predetermined low target temperature TLT; and reciprocating means to enable relative reciprocating motion between the holder and at least one bath while the reactor(s) is/are placed in the at least one bath, the relative reciprocating motion being executable by shaking the bath or the holder or both.
    Type: Application
    Filed: December 6, 2018
    Publication date: April 11, 2019
    Applicant: STAR ARRAY PTE LTD
    Inventors: Haiqing GONG, Yan WEN, Xudong ZENG
  • Publication number: 20190091694
    Abstract: A method and an apparatus for thermal processing of nucleic acid in a thermal profile. The method employs at least a first bath and a second bath, the method further employing a reactor holder for holding reactor(s) accommodating reaction material containing the nucleic acid. The method includes maintaining bath mediums in the baths at two different temperatures; and alternately allowing the reactor(s) to be in the two baths in a plurality of thermal cycles to alternately attain a predetermined high target temperature THT, and a predetermined low target temperature TLT, wherein the bath medium in at least one of the baths is a high thermal conductivity powder.
    Type: Application
    Filed: November 26, 2018
    Publication date: March 28, 2019
    Applicant: STAR ARRAY PTE LTD
    Inventors: Haiqing GONG, Yan WEN, Xudong ZENG