Patents by Inventor Yan Zhong

Yan Zhong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080028188
    Abstract: A receiver having an apparatus having a processor for processing interleaved data; and an independent memory coupled to the processor for processing the interleaved data is provided.
    Type: Application
    Filed: February 21, 2007
    Publication date: January 31, 2008
    Applicant: LEGEND SILICON
    Inventor: Yan Zhong
  • Patent number: 7266749
    Abstract: A method for constructing a simplified trellis diagram for BCH-encoded information is disclosed. BCH-encoded information is received, having a corresponding parity check matrix H. The parity check matrix H is expressed as an ordered sequence of columns of matrices. A sequence of sub-code words is provided, corresponding to one or more code words, each satisfying a given condition. A matrix Hcp, having columns that are generated as a selected permutation of the columns of the matrix H through a column-permutation-for-binary-matching process, is provided, and a sequence of sub-matrices and a corresponding sequence of permuted sub-code words is provided. A trellis diagram, representing an ordered sequence of code word transitions in the received information and symmetric about a central location, is provided for each code word c, connecting n+1 stages, numbered i=0, 1, . . . , n, in an ordered sequence.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: September 4, 2007
    Assignee: Legend Silicon Corporation
    Inventors: Yan Zhong, Lin Yang
  • Patent number: 6898757
    Abstract: A method for efficient decoding of block product code format signals, using a (22p)QAM signal constellation for mapping of a received signal, with p=2, 3, 4, 5, . . . A received signal value rx, corresponding to an x=I or x=Q coordinate, is converted to a p-tuple (B(p-1)x, . . . , B0x) corresponding to a “closest” I-coordinate or Q-coordinate numerical value, and a p-stage algorithm is applied to the signal values rx and to the p-tuples (B(p-1)x, . . . , B0x) to determine a p-tuple (r(p-1)x, . . . , r0x) representing a decoded p-bit value for the received signal value rx. Depending upon a communication channel parameter Eb/N0 and the bit error ratio BER associated with each of the p bits, the received signal values rx may be suitable for some or all communications activities (e.g., HDTV, SDTV, mobile comm).
    Type: Grant
    Filed: April 4, 2002
    Date of Patent: May 24, 2005
    Assignee: Legend Silicon Corporation
    Inventors: Yan Zhong, Lin Yang
  • Patent number: 6426982
    Abstract: Method and system for efficiently and quickly forming a sequence of convolution values from an over-sampled digital signal sequence. Convolution value differences are computable from a set of digital signal values that is smaller than the original set of signal values by a factor of R, the over-sampling rate. The number of adders and the associated time delay for computation of the convolution differences are reduced by at least a factor R and by at least a factor approximately proportional to log2(R), respectively, as compared to conventional computation of a convolution value. This approach is used to estimate a time value for which the convolution attains a largest magnitude or value.
    Type: Grant
    Filed: September 17, 1999
    Date of Patent: July 30, 2002
    Assignee: Cadonca Design Systems, Inc.
    Inventors: Lin Yang, Yan Zhong, Kevin Hwang
  • Patent number: 6157684
    Abstract: Described is an one bit matched filter for generating a sequences of correlations between a signal bit stream and a sample stream of n sample bits. The n sample bits are arranged in a rang of n bit positions n, n-1, . . . , 2, 1. Among the n sample bits, m boundary positions are defined based on the bit pattern of the sample stream, where m<n. At a specific time T(k), the m boundary positions are used to generate a Contribution (k) for a section of signal bits that are shifted into the n bit positions. At the time T(k), a Correlation (k) is generated by adding the Contribution (k) with the Correlation (k-1) that was generated at the previous time T(k-1).
    Type: Grant
    Filed: October 14, 1998
    Date of Patent: December 5, 2000
    Assignee: Cadence Design Systems, Inc.
    Inventors: Lin Yang, Yan Zhong, Manouchehr S. Rafie
  • Patent number: 5970104
    Abstract: A Viterbi decoder generates a branch metric table from first and second data signals taken at two sample times and provides selected branch metrics to an add/compare/select circuit in response to branch indices from a branch index generator. The branch metrics in the branch metric table are the sixteen combinations of the sum of the first and second parallel data signals at first and second sample times and the inverse of such signals. The branch index generator generates the branch indices in response to a received state from the add/compare/select circuit, convolutional code polynomials and the possible states of a radix-4 trellis. The add/compare/select generates a survivor path decision based on the selected branch metrics.
    Type: Grant
    Filed: March 19, 1997
    Date of Patent: October 19, 1999
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yan Zhong, Lin Yang, Manouchehr Rafie