Patents by Inventor Yanbo Xu
Yanbo Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230068886Abstract: There is disclosed a packaged semiconductor device comprising: a leadframe having a first thickness; the leadframe comprising a die pad; a semiconductor die thereabove; and epoxy therebetween and arranged to bond the semiconductor die to the die pad; wherein in at least one region under the semiconductor die, the die pad has a second thickness less than the first thickness; wherein the die pad has at least one through-hole in the at least one region; and wherein the epoxy fills the at least one through-hole and extends thereunder and laterally beyond the through-hole. Corresponding leadframes, and an associated method of manufacture are also disclosed.Type: ApplicationFiled: August 10, 2022Publication date: March 2, 2023Inventors: You Ge, Zhijie Wang, Yit Meng Lee, Yanbo Xu
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Patent number: 9613941Abstract: A semiconductor package has a lead frame and a power die. The lead frame has a first die paddle with a cavity formed entirely therethrough. The power die, which has a lower surface, is mounted on the first die paddle such that a first portion of the lower surface is attached to the first die paddle using a solderless die-attach adhesive, and a second portion of the lower surface, is not attached to the first die paddle and abuts the cavity formed in the first die paddle such that the second portion is exposed.Type: GrantFiled: November 24, 2014Date of Patent: April 4, 2017Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Yanbo Xu, Zhijie Wang, Fei Zong
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Patent number: 9362212Abstract: A packaged integrated circuit device includes a substrate module, leads, an IC die having first and second sets of die contact pads, and an encapsulant. The substrate module has upper and lower sets of conductive contacts on its upper and lower surfaces, respectively. The upper set of conductive contacts is electrically connected to the lower set of conductive contacts. The first set of die contact pads is electrically connected to the upper set of conductive contacts. The second set of die contact pads is electrically connected to the leads. Certain embodiments are a multi-form packaged device having both leads and conductive balls supporting different types of external connections, such as BGA and QFN.Type: GrantFiled: September 11, 2015Date of Patent: June 7, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Yanbo Xu, Jianshe Bi, Jinsheng Wang, Zhijie Wang, Fei Zong
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Patent number: 9252114Abstract: A grid array assembly is formed from an electrical insulating material with embedded solder deposits. A first portion of each of the solder deposits is exposed on a first surface of the insulating material and a second portion of each of the solder deposits is exposed on an opposite surface of the insulating material. A semiconductor die is mounted to the first surface of the insulating material and electrodes of the die are connected to the solder deposits with bond wires. The die, bond wires, and the first surface of the insulating material then are covered with a protective encapsulating material.Type: GrantFiled: November 23, 2014Date of Patent: February 2, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Zhijie Wang, Zhigang Bai, Aipeng Shu, Yanbo Xu, Huchang Zhang, Fei Zong
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Patent number: 9214413Abstract: A semiconductor die is packaged by providing a die assembly that includes a semiconductor die with an active surface and an opposite mounting surface with an attached thermally conductive substrate. The die assembly is mounted on a first surface of a lead frame die flag so that the thermally conductive substrate is sandwiched between the die flag and the semiconductor die. Bonding pads of the die are electrically connected with bond wires to lead frame lead fingers. A mold compound then encapsulates the semiconductor die, bond wires, and thermally conductive substrate. A second surface of the die flag is exposed through the mold compound.Type: GrantFiled: November 23, 2014Date of Patent: December 15, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Zhijie Wang, Zhigang Bai, Aipeng Shu, Yanbo Xu, Huchang Zhang, Fei Zong
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Patent number: 9196557Abstract: A method for packaging an integrated circuit (IC) device in which conventional manufacturing steps of mechanically bonding a die to a corresponding interconnecting substrate, wire bonding the die, and encapsulating the die in a protective shell are replaced by a single manufacturing step that includes thermally treating an appropriate assembly of parts to both form proper electrical connections for the die in the resulting IC package and cause the molding compound(s) to encapsulate the die in a protective enclosure.Type: GrantFiled: November 26, 2014Date of Patent: November 24, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Jianshe Bi, Lanping Bai, Quan Chen, Liping Guo, Yanbo Xu
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Publication number: 20150332985Abstract: A method for packaging an integrated circuit (IC) device in which conventional manufacturing steps of mechanically bonding a die to a corresponding interconnecting substrate, wire bonding the die, and encapsulating the die in a protective shell are replaced by a single manufacturing step that includes thermally treating an appropriate assembly of parts to both form proper electrical connections for the die in the resulting IC package and cause the molding compound(s) to encapsulate the die in a protective enclosure.Type: ApplicationFiled: November 26, 2014Publication date: November 19, 2015Inventors: Jianshe Bi, Lanping Bai, Quan Chen, Liping Guo, Yanbo Xu
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Publication number: 20150255443Abstract: A semiconductor package has a lead frame and a power die. The lead frame has a first die paddle with a cavity formed entirely therethrough. The power die, which has a lower surface, is mounted on the first die paddle such that a first portion of the lower surface is attached to the first die paddle using a solderless die-attach adhesive, and a second portion of the lower surface, is not attached to the first die paddle and abuts the cavity formed in the first die paddle such that the second portion is exposed.Type: ApplicationFiled: November 24, 2014Publication date: September 10, 2015Inventors: Yanbo Xu, Zhijie Wang, Fei Zong
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Publication number: 20150243623Abstract: A grid array assembly is formed from an electrical insulating material with embedded solder deposits. A first portion of each of the solder deposits is exposed on a first surface of the insulating material and a second portion of each of the solder deposits is exposed on an opposite surface of the insulating material. A semiconductor die is mounted to the first surface of the insulating material and electrodes of the die are connected to the solder deposits with bond wires. The die, bond wires, and the first surface of the insulating material then are covered with a protective encapsulating material.Type: ApplicationFiled: November 23, 2014Publication date: August 27, 2015Inventors: Zhijie Wang, Zhigang Bai, Aipeng Shu, Yanbo Xu, Huchang Zhang, Fei Zong
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Publication number: 20150243586Abstract: A semiconductor die is packaged by providing a die assembly that includes a semiconductor die with an active surface and an opposite mounting surface with an attached thermally conductive substrate. The die assembly is mounted on a first surface of a lead frame die flag so that the thermally conductive substrate is sandwiched between the die flag and the semiconductor die. Bonding pads of the die are electrically connected with bond wires to lead frame lead fingers. A mold compound then encapsulates the semiconductor die, bond wires, and thermally conductive substrate. A second surface of the die flag is exposed through the mold compound.Type: ApplicationFiled: November 23, 2014Publication date: August 27, 2015Inventors: Zhijie Wang, Zhigang Bai, Aipeng Shu, Yanbo Xu, Huchang Zhang, Fei Zong
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Patent number: 8652384Abstract: An apparatus for molding a semiconductor device includes an upper mold chase and a lower mold chase. The mold chases are capable of being aligned with each other, forming spaced cavities for receiving a lead frame array that includes semiconductor dies for encapsulation. The cavities are aligned in spaced, vertical columns and gates are provided at the opening of each column of cavities. A molding compound is passed through the gates and flows uninterrupted through each cavity and encapsulates the semiconductor dies.Type: GrantFiled: June 6, 2012Date of Patent: February 18, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Quan Chen, Wei Gai, Yanbo Xu
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Publication number: 20130005087Abstract: An apparatus for molding a semiconductor device includes an upper mold chase and a lower mold chase. The mold chases are capable of being aligned with each other, forming spaced cavities for receiving a lead frame array that includes semiconductor dies for encapsulation. The cavities are aligned in spaced, vertical columns and gates are provided at the opening of each column of cavities. A molding compound is passed through the gates and flows uninterrupted through each cavity and encapsulates the semiconductor dies.Type: ApplicationFiled: June 6, 2012Publication date: January 3, 2013Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Quan Chen, Wei Gao, Yanbo Xu