Abstract: A display substrate includes: a first base substrate; scanning lines at a side of the first base substrate, extending in a first direction and arranged in a second direction; data lines at the same side of the first base substrate as the scanning lines and in a different layer from the scanning lines, extending in the second direction and arranged in the first direction; a common electrode layer at a side of the scanning lines and the data lines facing away from the first base substrate; and a first light shielding layer in contact with the common electrode layer, and including first light shielding portions extending in the second direction. The first direction intersects with the second direction. The first light shielding portions are in areas between adjacent sub-pixels in the first direction.

Abstract: The present invention provides a BCMA-targeted chimeric antigen receptor (CAR) as well as a preparation method therefor and an application thereof. Specifically, the present invention provides the BCMA-targeted CAR, which comprises a BCMA-targeted scFv, a hinge region, a transmembrane region, and an intracellular signal structure domain. The present invention provides a nucleic acid molecule for coding the CAR and a corresponding expression vector as well as CAR-T cells and application thereof. The CAR of the present invention targets BCMA-positive cells, and can be used for treating BCMA-positive B-cell lymphoma, multiple myeloma and plasma cell leukemia.

Abstract: A display substrate, a display panel and a display device, including: a first base substrate, a first polarizer located on one side of the first base substrate, a data line located on a side, away from the first polarizer, of the first base substrate, and the extension direction of the data line is substantially perpendicular to the absorption axis of the first polarizer.

Abstract: Disclosed are a display substrate, a display substrate motherboard and a display apparatus. The display substrate includes a display region and a bonding region located on a side of the display region, wherein the bonding region includes a fanout region, the fanout region includes a first anti-static area and a first wiring area located around the first anti-static area, the first wiring area includes a plurality of fanout wires, the first anti-static area includes at least one electrostatic protection structure disposed between the plurality of fanout wires, and the electrostatic protection structure includes at least one pair of electrostatic protection lines, and the pair of electrostatic protection lines includes two electrostatic protection lines disposed symmetrically about a center line extending in a first direction.

Abstract: Provided are a chimeric antigen receptor targeting CD20 antigen and a preparation method thereof. The extracellular antigen binding domain of the chimeric antigen receptor includes an antibody heavy chain variable region shown in SEQ ID NO: 7 or 9 or 33 and an antibody light chain variable region shown in SEQ ID NO: 11 or 13 or 35, and is capable of killing tumor cells.

Abstract: The present disclosure provides bispecific chimeric antigen receptors targeting BCMA and CD19. The CAR may comprise an scFv targeting BCMA and an scFv targeting CD19, a hinge region, a transmembrane domain, a co-stimulatory region, and a cytoplasmic signaling domain. The chimeric antigen receptors can be used to treat autoimmune disorders or cancer.

Abstract: A method and system for generating a variable rate irrigation (VRI) prescription map for a large sprinkler irrigation system is provided. The method includes: determining a minimum length of a VRI management zone along a truss direction of the sprinkler irrigation system; determining a minimum angle of the VRI management zone along a travel direction of the sprinkler irrigation system; dividing the VRI management zone to generate a VRI management zoning map; determining, according to a basic irrigation amount of VRI management and a spatial distribution map of crop water deficit or a spatial distribution map of soil water holding capacity (SWHC), an irrigation quota of each management sub-zone; and generating, according to a distribution map of irrigation quotas of all management sub-zones in combination with a travel speed of the sprinkler irrigation system and a duty cycle of a solenoid valve, the VRI prescription map.

Abstract: A bidirectional DC/DC converter includes a first terminal circuit, a transformer, a second terminal circuit, and a reset circuit, and the transformer includes a first winding and a second winding. The first terminal circuit is coupled to the first winding, and the second terminal circuit and the reset circuit are coupled to the second winding. In a first time period in which the bidirectional DC/DC converter is in a second working state, the second terminal circuit transmits a second alternating current to the first terminal circuit by using the second winding and the first winding; and in a second time period in which the bidirectional DC/DC converter is in the second working state, the reset circuit is in a conducted state, to reset the second winding.

Abstract: The present invention provides a combined chimeric antigen receptor targeting CD19 and CD20 and application thereof. Specifically, the present invention provides a combined chimeric antigen receptor targeting CD19 and CD20, which comprises a scFv targeting CD19 and CD20, a hinge region, a transmembrane region, and an intracellular signaling domain. The present invention provides a nucleic acid molecule encoding the chimeric antigen receptor and a corresponding expression vector, a CAR-T cell, and applications thereof. The experimental results show that the chimeric antigen receptor provided by the present invention shows extremely high killing ability against tumor cells. The chimeric antigen receptor of the present invention targets CD19 and/or CD20 positive cells and can be used to treat CD19 and/or CD20 positive B-cell lymphoma, leukemia and other diseases.

Abstract: A display substrate, a display panel and a display device, including: a first base substrate, a first polarizer located on one side of the first base substrate, a data line located on a side, away from the first polarizer, of the first base substrate, and the extension direction of the data line is substantially perpendicular to the absorption axis of the first polarizer.

Abstract: An array substrate has sub-pixel regions arranged in an array, and the sub-pixel regions include white sub-pixel regions and primary color sub-pixel regions. The array substrate includes a first substrate and a plurality of sub-pixels disposed on the first substrate. The sub-pixels include white sub-pixels and primary color sub-pixels. In a column direction, a side of each white sub-pixel is adjacent to at least one primary color sub-pixel. Each sub-pixel has light-shielding patterns. In the column direction, in a plurality of light-shielding patterns of a primary color sub-pixel adjacent to the white sub-pixel, a part of the light-shielding patterns are disposed in a white sub-pixel region where the white sub-pixel is located, and another part of the light-shielding patterns are disposed in a primary color sub-pixel region corresponding to the primary color sub-pixel.

Abstract: A display panel is provided, which includes a first substrate and a second substrate arranged opposite to each other. The first substrate includes a first electrode and a second electrode. The second substrate includes a light shielding layer. The light shielding layer includes a light transmitting region and a light shielding region. The first electrode includes slits extending in a first direction, and an orthographic projection of two ends of at least one of the slits onto the first substrate is within an orthographic projection of the light shielding region onto the first substrate. A display panel and a display device are also provided.

Abstract: A display substrate includes: a first base substrate; scanning lines a side of the first base substrate, extending in a first direction; and arranged in a second direction data lines at the same side of the first base substrate as the scanning lines and in a different layers from the scanning lines, extending in the second direction and arranged in the first direction; a common electrode layer at a side of the scanning lines and the data lines facing away from the first base substrate; and a first light shielding layer in contact with the common electrode layer, and including first light shielding portions extending in the second direction. The first direction intersects with the second direction. The first light shielding portions are in areas between adjacent sub-pixels in the first direction.

Abstract: A common-mode voltage suppression method includes: selecting two large and two small vectors with low common-mode voltage magnitudes as basic voltage vectors; writing a volt-second balance equation according to a selected basic voltage vectors, and calculating, an introduced distribution factor of duty cycles of small vectors, initial values of distribution factors of a duty cycle of each basic voltage vector and of small vectors; designing a neutral-point voltage balance controller to obtain and utilize a corrected value of the distribution factor of the duty cycles of the small vectors and the initial values and combine with a set neutral-point voltage balance control threshold to update the duty cycle of each basic voltage vector; and inserting shoot-through states into the small vectors, designing a switching sequence, converting the sequence into a driving signal of a power switch, and controlling an operation of the quasi-Z-source simplified three-level inverter.

Abstract: An array substrate includes a substrate, signal lines, conductive bumps, an insulating layer, and thin film transistors each including a gate, source, and drain. The conductive blocks are disposed on a portion of the substrate located in a bonding region. The insulating layer is located between every two adjacent conductive bumps. A distance from a surface of a conductive metal layer included in a conductive bump away from the substrate to the substrate is less than or equal to a distance from a surface of the insulating layer away from the substrate to the substrate. The gate and signal lines are disposed in a same layer. The conductive metal layer is disposed in a same layer as the source and drain. On the substrate, an orthogonal projection of the conductive metal layer is located within an orthogonal projection of a signal line connected to the conductive metal layer.

Abstract: Disclosed are a display substrate, a display substrate motherboard and a display apparatus. The display substrate includes a display region and a bonding region located on a side of the display region, wherein the bonding region includes a fanout region, the fanout region includes a first anti-static area and a first wiring area located around the first anti-static area, the first wiring area includes a plurality of fanout wires, the first anti-static area includes at least one electrostatic protection structure disposed between the plurality of fanout wires, and the electrostatic protection structure includes at least one pair of electrostatic protection lines, and the pair of electrostatic protection lines includes two electrostatic protection lines disposed symmetrically about a center line extending in a first direction.

Abstract: A common-mode voltage suppression method includes: selecting two large and two small vectors with low common-mode voltage magnitudes as basic voltage vectors; writing a volt-second balance equation according to a selected basic voltage vectors, and calculating, an introduced distribution factor of duty cycles of small vectors, initial values of distribution factors of a duty cycle of each basic voltage vector and of small vectors; designing a neutral-point voltage balance controller to obtain and utilize a corrected value of the distribution factor of the duty cycles of the small vectors and the initial values and combine with a set neutral-point voltage balance control threshold to update the duty cycle of each basic voltage vector; and inserting shoot-through states into the small vectors, designing a switching sequence, converting the sequence into a driving signal of a power switch, and controlling an operation of the quasi-Z-source simplified three-level inverter.

Abstract: An array substrate has a display area and a bezel area located on at least one side of the display area. The bezel area includes a bonding region. The array substrate includes a substrate, a plurality of signal lines, a plurality of conductive bumps, and an insulating layer. The signal lines are disposed on the substrate. The conductive blocks are disposed on a portion of the substrate located in the bonding region, and a conductive bump is connected to at least one signal line. The insulating layer covers the plurality of signal lines and is located between every two adjacent conductive bumps. The conductive bump includes a conductive metal layer. A distance from a surface of the conductive metal layer away from the substrate to the substrate is less than or equal to a distance from a surface of the insulating layer away from the substrate to the substrate.

Abstract: A display panel is provided, which includes a first substrate and a second substrate arranged opposite to each other. The first substrate includes a first electrode and a second electrode. The second substrate includes a light shielding layer. The light shielding layer includes a light transmitting region and a light shielding region. The first electrode includes slits extending in a first direction, and an orthographic projection of two ends of at least one of the slits onto the first substrate is within an orthographic projection of the light shielding region onto the first substrate. A display panel and a display device are also provided.

Abstract: A pixel electrode, including: a plurality of strip-shaped first electrodes, where the plurality of the first electrodes are arranged along a first direction, each of the first electrodes extends along a second direction, and the second direction intersects with the first direction; a second electrode, where the second electrode is connected to first ends of the plurality of first electrodes, and the first ends of the plurality of first electrodes are connected through the second electrode; and a third electrode, where the third electrode is connected to a second end of at least one of the first electrodes, and a direction of an electric field of an area in which the third electrode is disposed intersects with both the first direction and the second direction.