Patents by Inventor Yanfeng Li

Yanfeng Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12222622
    Abstract: An array substrate has sub-pixel regions arranged in an array, and the sub-pixel regions include white sub-pixel regions and primary color sub-pixel regions. The array substrate includes a first substrate and a plurality of sub-pixels disposed on the first substrate. The sub-pixels include white sub-pixels and primary color sub-pixels. In a column direction, a side of each white sub-pixel is adjacent to at least one primary color sub-pixel. Each sub-pixel has light-shielding patterns. In the column direction, in a plurality of light-shielding patterns of a primary color sub-pixel adjacent to the white sub-pixel, a part of the light-shielding patterns are disposed in a white sub-pixel region where the white sub-pixel is located, and another part of the light-shielding patterns are disposed in a primary color sub-pixel region corresponding to the primary color sub-pixel.
    Type: Grant
    Filed: September 14, 2023
    Date of Patent: February 11, 2025
    Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xueqiang Qian, Dongchuan Chen, Yanfeng Li, Yu Xing, Kaixuan Wang, Bingyang Liu
  • Patent number: 12216370
    Abstract: A display panel is provided, which includes a first substrate and a second substrate arranged opposite to each other. The first substrate includes a first electrode and a second electrode. The second substrate includes a light shielding layer. The light shielding layer includes a light transmitting region and a light shielding region. The first electrode includes slits extending in a first direction, and an orthographic projection of two ends of at least one of the slits onto the first substrate is within an orthographic projection of the light shielding region onto the first substrate. A display panel and a display device are also provided.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: February 4, 2025
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jing Li, Yanan Yu, Zhao Liu, Rui Fan, Xiao Yan, Haoyi Xin, Jianxiong Fan, Shangpeng Liu, Jingjing Xu, Min Zhang, Wei Ren, Chenrong Qiao, Yanfeng Li
  • Publication number: 20250035997
    Abstract: A display substrate includes: a first base substrate; scanning lines a side of the first base substrate, extending in a first direction; and arranged in a second direction data lines at the same side of the first base substrate as the scanning lines and in a different layers from the scanning lines, extending in the second direction and arranged in the first direction; a common electrode layer at a side of the scanning lines and the data lines facing away from the first base substrate; and a first light shielding layer in contact with the common electrode layer, and including first light shielding portions extending in the second direction. The first direction intersects with the second direction. The first light shielding portions are in areas between adjacent sub-pixels in the first direction.
    Type: Application
    Filed: December 24, 2021
    Publication date: January 30, 2025
    Inventors: Lei YAO, Yongqiang ZHANG, Haoyi XIN, Jingyi XU, Feng LI, Yanfeng LI
  • Patent number: 12184160
    Abstract: A common-mode voltage suppression method includes: selecting two large and two small vectors with low common-mode voltage magnitudes as basic voltage vectors; writing a volt-second balance equation according to a selected basic voltage vectors, and calculating, an introduced distribution factor of duty cycles of small vectors, initial values of distribution factors of a duty cycle of each basic voltage vector and of small vectors; designing a neutral-point voltage balance controller to obtain and utilize a corrected value of the distribution factor of the duty cycles of the small vectors and the initial values and combine with a set neutral-point voltage balance control threshold to update the duty cycle of each basic voltage vector; and inserting shoot-through states into the small vectors, designing a switching sequence, converting the sequence into a driving signal of a power switch, and controlling an operation of the quasi-Z-source simplified three-level inverter.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: December 31, 2024
    Assignee: SHANDONG JIANZHU UNIVERSITY
    Inventors: Changwei Qin, Xiaoyan Li, Zhiyuan Chu, Hongliang Zhang, Yanfeng Li
  • Publication number: 20240411184
    Abstract: An array substrate includes a substrate, signal lines, conductive bumps, an insulating layer, and thin film transistors each including a gate, source, and drain. The conductive blocks are disposed on a portion of the substrate located in a bonding region. The insulating layer is located between every two adjacent conductive bumps. A distance from a surface of a conductive metal layer included in a conductive bump away from the substrate to the substrate is less than or equal to a distance from a surface of the insulating layer away from the substrate to the substrate. The gate and signal lines are disposed in a same layer. The conductive metal layer is disposed in a same layer as the source and drain. On the substrate, an orthogonal projection of the conductive metal layer is located within an orthogonal projection of a signal line connected to the conductive metal layer.
    Type: Application
    Filed: August 22, 2024
    Publication date: December 12, 2024
    Inventors: Yanyong SONG, Yanfeng LI, Haoyi XIN, Xu QIAO, Chenrong QIAO, Wei REN, Yu XING, Jingjing XU, Rula SHA, Guolei ZHI, Guangshuai WANG, Liwen XIN, Jingwei HOU
  • Publication number: 20240355831
    Abstract: Disclosed are a display substrate, a display substrate motherboard and a display apparatus. The display substrate includes a display region and a bonding region located on a side of the display region, wherein the bonding region includes a fanout region, the fanout region includes a first anti-static area and a first wiring area located around the first anti-static area, the first wiring area includes a plurality of fanout wires, the first anti-static area includes at least one electrostatic protection structure disposed between the plurality of fanout wires, and the electrostatic protection structure includes at least one pair of electrostatic protection lines, and the pair of electrostatic protection lines includes two electrostatic protection lines disposed symmetrically about a center line extending in a first direction.
    Type: Application
    Filed: December 28, 2021
    Publication date: October 24, 2024
    Inventors: Jingyi XU, Jianyun XIE, Wei LI, Jian SUN, Zhen WANG, Yanqing CHEN, Yanfeng LI, Lin HOU, Aiyu DING, Jiantao LIU
  • Publication number: 20240348152
    Abstract: A common-mode voltage suppression method includes: selecting two large and two small vectors with low common-mode voltage magnitudes as basic voltage vectors; writing a volt-second balance equation according to a selected basic voltage vectors, and calculating, an introduced distribution factor of duty cycles of small vectors, initial values of distribution factors of a duty cycle of each basic voltage vector and of small vectors; designing a neutral-point voltage balance controller to obtain and utilize a corrected value of the distribution factor of the duty cycles of the small vectors and the initial values and combine with a set neutral-point voltage balance control threshold to update the duty cycle of each basic voltage vector; and inserting shoot-through states into the small vectors, designing a switching sequence, converting the sequence into a driving signal of a power switch, and controlling an operation of the quasi-Z-source simplified three-level inverter.
    Type: Application
    Filed: December 28, 2022
    Publication date: October 17, 2024
    Applicant: SHANDONG JIANZHU UNIVERSITY
    Inventors: Changwei QIN, Xiaoyan LI, Zhiyuan CHU, Hongliang ZHANG, Yanfeng LI
  • Patent number: 12105383
    Abstract: An array substrate has a display area and a bezel area located on at least one side of the display area. The bezel area includes a bonding region. The array substrate includes a substrate, a plurality of signal lines, a plurality of conductive bumps, and an insulating layer. The signal lines are disposed on the substrate. The conductive blocks are disposed on a portion of the substrate located in the bonding region, and a conductive bump is connected to at least one signal line. The insulating layer covers the plurality of signal lines and is located between every two adjacent conductive bumps. The conductive bump includes a conductive metal layer. A distance from a surface of the conductive metal layer away from the substrate to the substrate is less than or equal to a distance from a surface of the insulating layer away from the substrate to the substrate.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: October 1, 2024
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yanyong Song, Yanfeng Li, Haoyi Xin, Xu Qiao, Chenrong Qiao, Wei Ren, Yu Xing, Jingjing Xu, Rula Sha, Guolei Zhi, Guangshuai Wang, Liwen Xin, Jingwei Hou
  • Publication number: 20240288735
    Abstract: A display panel is provided, which includes a first substrate and a second substrate arranged opposite to each other. The first substrate includes a first electrode and a second electrode. The second substrate includes a light shielding layer. The light shielding layer includes a light transmitting region and a light shielding region. The first electrode includes slits extending in a first direction, and an orthographic projection of two ends of at least one of the slits onto the first substrate is within an orthographic projection of the light shielding region onto the first substrate. A display panel and a display device are also provided.
    Type: Application
    Filed: May 11, 2022
    Publication date: August 29, 2024
    Applicants: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jing Li, Yanan Yu, Zhao Liu, Rui Fan, Xiao Yan, Haoyi Xin, Jianxiong Fan, Shangpeng Liu, Jingjing Xu, Min Zhang, Wei Ren, Chenrong Qiao, Yanfeng Li
  • Patent number: 12072586
    Abstract: A pixel electrode, including: a plurality of strip-shaped first electrodes, where the plurality of the first electrodes are arranged along a first direction, each of the first electrodes extends along a second direction, and the second direction intersects with the first direction; a second electrode, where the second electrode is connected to first ends of the plurality of first electrodes, and the first ends of the plurality of first electrodes are connected through the second electrode; and a third electrode, where the third electrode is connected to a second end of at least one of the first electrodes, and a direction of an electric field of an area in which the third electrode is disposed intersects with both the first direction and the second direction.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: August 27, 2024
    Assignees: Ordos Yuansheng Optoelectronics Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Wei Ren, Wei Li, Yanfeng Li, Haoyi Xin, Jing Li, Jingjing Xu, Chenrong Qiao, Yanyong Song, Xu Qiao, Rula Sha, Min Zhang
  • Patent number: 12002887
    Abstract: The embodiments of the present disclosure provide an array substrate and a method for manufacturing the same, and a display device. The array substrate includes a substrate, wherein the substrate has a display region and a peripheral region surrounding the display region, the display region has a plurality of pixels arranged in an array, and each of the plurality of pixels includes a light transmission region and a light shielding region, and a light shielding block covering at least a part of the light transmission region of at least one pixel close to the peripheral region of the plurality of pixels.
    Type: Grant
    Filed: June 28, 2023
    Date of Patent: June 4, 2024
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yanqing Chen, Jianyun Xie, Wei Li, Cheng Li, Pan Guo, Yanfeng Li, Weida Qin, Ning Wang
  • Publication number: 20240170503
    Abstract: An array substrate, a liquid crystal display panel and a display apparatus. The array substrate comprises: a substrate (10), a first insulating layer (20), a second insulating layer (30), a third insulating layer (40), a planarization layer (50), a first electrode layer (90A), a fourth insulating layer (70) and a second electrode layer (90B), the third insulating layer comprises a first interlayer insulating layer (40A), a second interlayer insulating layer (40B) and a third interlayer insulating layer (40C), which are sequentially stacked; the first interlayer insulating layer is located on the side of the second interlayer insulating layer close to the substrate (10), the third interlayer insulating layer is located on the side of the second interlayer insulating layer away from the substrate; the material of the first interlayer insulating layer and third interlayer insulating layer comprises silicon oxide, the material of the second interlayer insulating layer comprises silicon nitride.
    Type: Application
    Filed: October 31, 2022
    Publication date: May 23, 2024
    Inventors: Haoyi XIN, Wei LI, Yanfeng LI, Jingjing XU, Min ZHANG, Rui FAN, Chenrong QIAO, Xiao YAN, Zhao LIU, Jing LI, Jianxiong FAN, Shangpeng LIU, Haidong SU
  • Publication number: 20240139243
    Abstract: The present invention provides a combined chimeric antigen receptor targeting CD19 and CD20 and application thereof. Specifically, the present invention provides a combined chimeric antigen receptor targeting CD19 and CD20, which comprises a scFv targeting CD19 and CD20, a hinge region, a transmembrane region, and an intracellular signaling domain. The present invention provides a nucleic acid molecule encoding the chimeric antigen receptor and a corresponding expression vector, a CAR-T cell, and applications thereof. The experimental results show that the chimeric antigen receptor provided by the present invention shows extremely high killing ability against tumor cells. The chimeric antigen receptor of the present invention targets CD19 and/or CD20 positive cells and can be used to treat CD19 and/or CD20 positive B-cell lymphoma, leukemia and other diseases.
    Type: Application
    Filed: March 14, 2023
    Publication date: May 2, 2024
    Inventors: Yihong YAO, Yanfeng LI, Yutian WEI, Shigui ZHU, Xin YAO, Jiaqi HUANG
  • Publication number: 20240122135
    Abstract: A method and system for generating a variable rate irrigation (VRI) prescription map for a large sprinkler irrigation system is provided. The method includes: determining a minimum length of a VRI management zone along a truss direction of the sprinkler irrigation system; determining a minimum angle of the VRI management zone along a travel direction of the sprinkler irrigation system; dividing the VRI management zone to generate a VRI management zoning map; determining, according to a basic irrigation amount of VRI management and a spatial distribution map of crop water deficit or a spatial distribution map of soil water holding capacity (SWHC), an irrigation quota of each management sub-zone; and generating, according to a distribution map of irrigation quotas of all management sub-zones in combination with a travel speed of the sprinkler irrigation system and a duty cycle of a solenoid valve, the VRI prescription map.
    Type: Application
    Filed: February 10, 2023
    Publication date: April 18, 2024
    Applicant: China Institute of Water Resources and Hydropower Research
    Inventors: Weixia ZHAO, Baozhong ZHANG, Zhijie SHAN, Jiusheng LI, Minne ZHANG, Changxin ZHU, Yanfeng LI
  • Patent number: 11944048
    Abstract: A decision-making method for variable rate irrigation management includes the following steps: S1: sampling a soil from a root zone of a crop in an area controlled by an irrigation sprinkler, and measuring compositions of separates of the sampled soil; S2: managing and dividing the area controlled by the irrigation sprinkler according to an AWC of the soil in the root zone of the crop; S3: constructing an optimized soil moisture sensor network; S4: placing ground-fixed canopy temperature sensors; S5: constructing an optimized airborne canopy temperature sensor network centered on the center pivot; and S6: performing a variable rate irrigation by using the optimized soil moisture sensor network, the fixed canopy temperature sensors, the optimized airborne canopy temperature sensor network and an automatic weather station. The method optimizes the placement and quantity of the soil moisture sensor network and the canopy temperature sensor network to improve the measurement accuracy.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: April 2, 2024
    Assignee: CHINA INSTITUTE OF WATER RESOURCES AND HYDROPOWER RESEARCH
    Inventors: Weixia Zhao, Jiusheng Li, Yanfeng Li, Zhen Wang, Jun Wang
  • Patent number: 11942577
    Abstract: An optical device includes an LED chip, a light absorber and/or visible-light luminescent material, and a near-infrared luminescent material, wherein a luminous power of light emitted by the near-infrared luminescent material and the light absorber and/or visible-light luminescent material in a band of 650-1000 nm under the excitation of the LED chip is A, and a sum of a luminous power of light emitted by the near-infrared and visible-light luminescent materials in a band of 350-650 nm under the excitation of the LED chip and a luminous power of residual light emitted by the LED chip in the band of 350-650 nm after the LED chip excites the near-infrared and visible-light luminescent materials is B, with B/A*100% being 0.1%-10%. According to the implementation where the optical device employs the LED chip to combine the near-infrared luminescent material and the light absorber and/or visible-light luminescent material simultaneously.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: March 26, 2024
    Assignee: GRIREM ADVANCED MATERIALS CO., LTD.
    Inventors: Ronghui Liu, Yuanhong Liu, Yanfeng Li, Xiaoxia Chen, Xiaole Ma, Yuan Xue
  • Patent number: 11932793
    Abstract: The invention relates to a phosphor with garnet structure and a light-emitting device comprising the phosphor, wherein the phosphor includes the following components in percentage by weight: 38.47-45.19% of Y element, 9.49-22.09% of Al element, 2.06-24.31% of Ga element, 27.3-32.04% of O element, 0.43-1.46% of Ce element. In the phosphor particles, the shortest distance from the surface of one side of the particle to the surface of the opposite side through the centroid of the particle is defined as R, the longest distance is R1, and 5 ?m?R?40 ?m; any distance from the particle surface to the centroid is r, and 0<r<½R; and the space with the distance from the particle surface to the centroid direction being less than or equal to r is defined as rinner.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: March 19, 2024
    Assignees: GRIREM ADVANCED MATERIALS CO., LTD., Grirem Hi-Tech Co., Ltd, Rare Earth Functional Materials (Xiong'an) Innovation Center Co., Ltd.
    Inventors: Ronghui Liu, Shaowei Qin, Yuanhong Liu, Yanfeng Li, Xiaoxia Chen, Xiaole Ma, Yuan Xue
  • Publication number: 20240004247
    Abstract: An array substrate has sub-pixel regions arranged in an array, and the sub-pixel regions include white sub-pixel regions and primary color sub-pixel regions. The array substrate includes a first substrate and a plurality of sub-pixels disposed on the first substrate. The sub-pixels include white sub-pixels and primary color sub-pixels. In a column direction, a side of each white sub-pixel is adjacent to at least one primary color sub-pixel. Each sub-pixel has light-shielding patterns. In the column direction, in a plurality of light-shielding patterns of a primary color sub-pixel adjacent to the white sub-pixel, a part of the light-shielding patterns are disposed in a white sub-pixel region where the white sub-pixel is located, and another part of the light-shielding patterns are disposed in a primary color sub-pixel region corresponding to the primary color sub-pixel.
    Type: Application
    Filed: September 14, 2023
    Publication date: January 4, 2024
    Inventors: Xueqiang QIAN, Dongchuan CHEN, Yanfeng LI, Yu XING, Kaixuan WANG, Bingyang LIU
  • Publication number: 20230369985
    Abstract: A bidirectional DC/DC converter includes a first terminal circuit, a transformer, a second terminal circuit, and a reset circuit, and the transformer includes a first winding and a second winding. The first terminal circuit is coupled to the first winding, and the second terminal circuit and the reset circuit are coupled to the second winding. In a first time period in which the bidirectional DC/DC converter is in a second working state, the second terminal circuit transmits a second alternating current to the first terminal circuit by using the second winding and the first winding; and in a second time period in which the bidirectional DC/DC converter is in the second working state, the reset circuit is in a conducted state, to reset the second winding.
    Type: Application
    Filed: July 28, 2023
    Publication date: November 16, 2023
    Inventors: Yanfeng Li, Yu Ma, Yongsheng Zhou
  • Publication number: 20230343874
    Abstract: The embodiments of the present disclosure provide an array substrate and a method for manufacturing the same, and a display device. The array substrate includes a substrate, wherein the substrate has a display region and a peripheral region surrounding the display region, the display region has a plurality of pixels arranged in an array, and each of the plurality of pixels includes a light transmission region and a light shielding region, and a light shielding block covering at least a part of the light transmission region of at least one pixel close to the peripheral region of the plurality of pixels.
    Type: Application
    Filed: June 28, 2023
    Publication date: October 26, 2023
    Inventors: Yanqing CHEN, Jianyun XIE, Wei LI, Cheng LI, Pan GUO, Yanfeng LI, Weida QIN, Ning WANG