Abstract: A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

Abstract: A metal oxide semiconductor, MOS, device (405) is described that includes a gate terminal, at least one source terminal and at least one drain terminal, wherein at least one source terminal and at least one drain terminal are formed of metal and are connected to a number of respective contact vias.

Abstract: The display substrate includes a substrate, multiple sub-pixels, multiple data lines, multiple power lines, multiple data signal input lines, multiple selector switches, a first power bus located in a peripheral area and on a side, facing away from the display area, of the multiple selector switches, and multiple power connection cables located in the peripheral area and between the first power bus and the multiple power lines. The multiple power connection cables are electrically connected with the first power bus and the multiple power lines.

Abstract: An array substrate is provided. The array substrate includes a base substrate and a plurality of gate lines, a plurality of data lines, a common electrode layer and a plurality of pixel units arranged in an array disposed on the base substrate. Each of the pixel units includes a plurality of sub-pixel units defined by gate lines and data lines disposed to intersect each other laterally and vertically. The common electrode layer includes a plurality of common electrode blocks that double as self-capacitance electrodes, each of the common electrode blocks is connected with at least one wire, and the wires are in the middle of sub-pixel units of a same column.

Abstract: A semiconductor device with different configurations of nanostructured channel regions and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a fin structure disposed on a substrate, a stack of nanostructured horizontal channel (NHC) regions disposed on the fin structure, a nanostructured vertical channel (NVC) region disposed within the stack of NHC regions, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the NHC regions and on portions of the NVC region that are not covered by the NHC regions and the fin structure.

Abstract: A semiconductor device includes a first source/drain, a second source/drain isolated from direct contact with the first source/drain in a horizontal direction, a channel extending between the first source/drain and the second source/drain, a gate surrounding the channel, an upper inner spacer between the gate and the first source/drain and above the channel, and a lower inner spacer between the gate and the first source/drain and under the channel, in which the channel includes a base portion extending between the first source/drain and the second source/drain, an upper protrusion portion protruding upward from a top surface of the base portion, and a lower protrusion portion protruding downward from a bottom surface of the base portion, and a direction in which a top end of the upper protrusion portion is isolated from direct contact with a bottom end of the lower protrusion portion is oblique with respect to a vertical direction.

Abstract: Discussed is an assembly chamber containing a fluid. The assembly chamber includes a bottom portion, a side wall portion formed at a predetermined height on the bottom portion and disposed to surround the bottom portion, and a partition wall part formed on the bottom portion and extending from one inner surface of a plurality of inner surfaces provided in the side wall portion to another inner surface facing the one inner surface. The vertical height of at least a portion of the partition wall part is variable with respect to the bottom portion.

Abstract: A light-emitting diode includes an epitaxial layered structure and a conductive mirror structure which includes a first electrically conductive layer and a second electrically conductive layer disposed on the epitaxial layered structure in such order. The first and second electrically conductive layers respectively have a first reflectance R1 and a second reflectance R2 to light emitted from the epitaxial layered structure, and R1<R2.

Abstract: This application relates to the battery field, and specifically, to an electrode plate, an electrochemical device, and an apparatus. The electrode plate of this application includes a current collector and an electrode active material layer disposed on at least one surface of the current collector, where the current collector includes a support layer and a conductive layer disposed on at least one surface of the support layer, a single-sided thickness D2 of the conductive layer satisfies 30 nm?D2?3 ?m, the support layer is made of a polymer material or a polymer composite material, and a thickness D1 of the support layer satisfies 1 ?m?D1?30 ?m; and the electrode active material layer includes an electrode active material, a binder, and a conductive agent.

Abstract: A battery module includes a battery module, which includes a battery unit and a casing for receiving the battery unit. The casing includes a first casing body, a second casing body assembled to the first casing body, and a first sealing ring disposed between the first casing body and the second casing body. The first casing body includes a first cover plate and first sidewalls connected to edges of the first cover plate. A slot is defined on outer surface of the first sidewalls. The second casing body includes a second cover plate and second sidewalls connected to edges of the second cover plate. A latch is disposed at inner surface of the second sidewalls, corresponding to the slot. The latch is configured to be received in the slot, locating and sealing the second cover plate on the first cover plate by compressing the first sealing ring.

Abstract: An electronic device comprises: a housing including a front plate, a rear plate, and side portions surrounding a space formed by the front plate and the rear plate; a display visible through the front plate; and an antenna module disposed in the space, wherein the antenna module comprises: a printed circuit board (PCB) including a first surface facing a first direction and a second surface facing a second direction opposite to the first direction; at least one first antenna disposed on the first surface of the PCB; an IC chip disposed on the second surface of the PCB; an insulation member comprising an insulating material covering at least a portion of the IC chip; and a second antenna disposed on a surface of the insulation member facing the second direction, wherein the IC chip may be configured to feed the first antenna, the first antenna may be configured to radiate a first signal of a first frequency band, and the second antenna may be configured to radiate a second signal.

Abstract: Provided are stretchable electronics and a method for manufacturing the same. The stretchable electronics may include a substrate, a plurality of electronic elements disposed to be spaced apart from each other on the substrate, and a wire structure disposed on the substrate to connect the plurality of electronic elements to each other. The wire structure may include an insulator extending from one of the electronic elements to the other of the adjacent electronic elements and a metal wire configured to cover a top surface and side surfaces of the insulator. The insulator may include at least one bent part in a plan view.

Abstract: Methods and apparatus for a lift pin mechanism for substrate processing chambers are provided herein. In some embodiments, the lift pin mechanism includes a lift pin comprising a shaft with a top end, a bottom end, and a coupling end at the bottom end; a bellows assembly disposed about the shaft. The bellows assembly includes an upper bellows flange having an opening for axial movement of the shaft; a bellows having a first end coupled to a lower surface of the upper bellows flange such that the shaft extends into a central volume surrounded by the bellows; and a bellows guide assembly coupled to a second end of the bellows to seal the central volume. The shaft is coupled to the bellows guide assembly at the coupling end. The bellows guide assembly is axially movable to move the lift pin with respect to the upper bellows flange.

Abstract: An interconnect structure and methods of forming the same are described. In some embodiments, the structure includes a first dielectric layer and one or more first conductive features disposed in the first dielectric layer. The one or more first conductive features includes a first metal. The structure further includes a plurality of graphene layers disposed on each of the one or more first conductive features, the plurality of graphene layers include a second metal intercalated therebetween, and the second metal is different from the first metal.

Abstract: A driving backplane, a display panel and a display device are provided. The driving backplane has a pixel circuit, a data line and a power line; transistors include a driving transistor, a writing transistor, a compensation transistor and an initialization transistor; the power line includes a power line body extending along a column direction and a shielding part connected to a side of the power line body along a row direction; at least a portion of the writing transistor and the initialization transistor are located between the power line and the data line; a channel of the driving transistor overlaps with the power line; and a channel of the compensation transistor overlaps with the shielding part.

Abstract: Methods and apparatus for graphics processing, such as producing a smooth transition between images of different dynamic ranges (e.g., Standard Dynamic Range (SDR) images and High Dynamic Range (HDR) images). An example method generally includes using a high frame rate during a transition period to allow properties of images to incrementally vary. The properties may include brightness (i.e., luminance), color gamut, tone mapping, among others. For example, during the transition period, a subset of HDR images are displayed at a second frame rate (e.g., 120 Hz) higher than a frame rate based on the HDR images (e.g., 30 Hz). Simultaneously, a brightness level (as well as other aspects) of the display panel is adjusted incrementally from an SDR brightness level to an HDR brightness level during the transition time period over the subset of the HDR images.

Abstract: One or more computer processors obtain an initial subnetwork at a target sparsity and an initial pruning mask from a pre-trained self-supervised learning (SSL) speech model. The one or more computer processors finetune the initial subnetwork, comprising: the one or more computer processors zero out one or more masked weights in the initial subnetwork specified by the initial pruning mask; the one or more computer processors train a new subnetwork from the zeroed out subnetwork; the one or more computer processors prune one or more weights of lowest magnitude in the new subnetwork regardless of network structure to satisfy the target sparsity. The one or more computer processors classify an audio segment with the finetuned subnetwork.

Abstract: Embodiments of the present disclosure provide a voice wake-up method, apparatus, electronic device, and readable storage medium. The method includes: acquiring a deep feature encoded by a voice activity detection (VAD) encoding layer through a VAD decoding layer, the deep feature being extracted from a digital audio signal used for VAD encoding and voice wake-up encoding; determining whether each audio segment in the digital audio signal is a voice according to a probability that each audio frame in the digital audio signal is a voice frame, each audio segment including a plurality of audio frames; and when determining that the audio segment is the voice, indicating, by the VAD decoding layer, to input a deep feature of the audio segment into a voice wake-up decoding layer to perform voice wake-up. The embodiments of the present disclosure improve the accuracy of voice wake-up.

Abstract: A system, method, and apparatus for improving communication between mobile or wearable devices and access points of the wireless land area network. The method includes sensing at a client station a service set identifier for a wireless access network. The method also includes determining a subset of channels within the wireless access network by accessing information stored in a database, and determining a scan time interval associated with the service set identifier by accessing the information stored in the database. In addition, the method includes transmitting a probe request through the subset of channels to an access point located within the wireless access network and receiving a probe response at the client station from the access point during the scan time interval. Further, the method includes identifying location of the client station based on the probe response.

Abstract: A resource indication method includes generating, by an access point, resource mapping information, where the resource mapping information includes a plurality of mapping segments, each mapping segment is associated with a frame type, each mapping segment includes a plurality of resource indicators, and each resource indicator indicates a resource allocated to a station in a frame corresponding to a frame type associated with a mapping segment to which the resource indicator belongs, and sending, by the access point, the resource mapping information.