Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature to a through-substrate via includes forming a self-aligned alignment feature having a wall around at least a portion of the TSV and aligning a photolithography tool to the self-aligned alignment feature. In some embodiments, the self-aligned alignment feature is defined by the topography of a seed material at a backside of the device.

Abstract: A polyelectrolyte includes a first segment and a second segment, wherein the structure of the first segment is at least one of formula (1) and formula (2); the structure of the second segment is at least one of formula (3) and formula (4). The polyelectrolyte undergoes microphase separation to form a nanoscale ordered self-assembled microstructure.

Abstract: The invention provides histone deacetylase (HDAC) inhibitors shown as Formula I, where R1 to R8 are as defined in the specification. The invention also provides methods for synthesis of these compounds and applications of these compounds in preparing pharmaceuticals for preventing or treating mammal diseases related to the dysregulation of HDAC.

Abstract: The invention provides histone deacetylase (HDAC) inhibitors shown as Formula I, where R1 to R8 are as defined in the specification. The invention also provides methods for synthesis of these compounds and applications of these compounds in preparing pharmaceuticals for preventing or treating mammal diseases related to the dysregulation of HDAC.

Abstract: A data processing system is disclosed. The system includes a processor, a transformer, a first memory buffer, a second memory buffer, a first filter, and a second filter. An obtained transmission signal symbol is first transformed to first data. The first memory buffer stores the first data. The processor obtains peak data based on the first data according to a predetermined threshold. The transformer transforms the peak data to second data and stores the second data in the second memory buffer. The first filter filters the second data to determine reserved data of the second data and removes the reserved data from the second data to generate third data. The transformer transforms the third data to fourth data and stores the fourth data in the second memory buffer. The processor merges the first and fourth data to generate fifth data. The second filter filters the fifth data based on the transmission signal symbol and a previously obtained transmission signal symbol.

Abstract: An optical storage medium recording apparatus is provided a data preparing and ECC encoding circuit that both prepares the data by combining different categories of data into data sequences in accordance with a data layout on the optical storage medium and encodes the combined data. The encoded data is temporarily stored in a data buffer, and subsequently successively read out by a recording circuit for recording onto the optical storage medium according to the data layout. For a Blu-ray disc recording apparatus, the data preparing and ECC encoding circuit includes a LDC/BIS encoder for generating long distance error correction codes (LDC) and burst indicator subcodes (BIS) from the combined data to form LDC and BIS encoded data, which is temporarily stored in the data buffer. The recording circuit includes an interleave circuit for interleaving the LDC and BIS data to form physical clusters for recording on the disc.

Abstract: A data processing system is disclosed. The system includes a processor, a transformer, a first memory buffer, a second memory buffer, a first filter, and a second filter. An obtained transmission signal symbol is first transformed to first data. The first memory buffer stores the first data. The processor obtains peak data based on the first data according to a predetermined threshold. The transformer transforms the peak data to second data and stores the second data in the second memory buffer. The first filter filters the second data to determine reserved data of the second data and removes the reserved data from the second data to generate third data. The transformer transforms the third data to fourth data and stores the fourth data in the second memory buffer. The processor merges the first and fourth data to generate fifth data. The second filter filters the fifth data based on the transmission signal symbol and a previously obtained transmission signal symbol.

Abstract: Disclosed are a method for writing data into a first storage on a chip and a system thereof. The method includes storing an initial firmware into a second storage on the chip, programming the first storage according to a specific data by utilizing the initial firmware, and blocking further programming operations applied to at least part of the specific data after the specific data is successfully stored in the first storage. Therefore the invention can save the external pin connections of the chip to prevent computer hackers from accessing or changing the content of the storage.

Abstract: In a method and apparatus for generating optimum write power, a control unit controls a write voltage generating unit to generate sequentially write voltages of different levels to drive an optical read/write head to generate different write powers so as to write data on a plurality of write intervals of an optical recording medium in sequence. Simultaneously, a detecting and computing circuit detects a peak value, a first level and a second level of a write reflected signal generated by each write interval for computation so as to obtain a first control parameter of each write interval, and detects a peak value, a bottom value and a direct current level of a read reflected signal generated during reading of each write interval for computation so as to obtain a second control parameter of each write interval, thereby generating an optimum write power based on optimal first and second control parameters.

Abstract: A programmable system for storage of one-time programmable information comprises an interface translator and a one-time programmable device. The interface translator receives and translates a command code to program code comprising a sequence of write instructions and a designated data block. The one-time programmable device is coupled to the interface translator, programmed by the write instructions to store the designated data block. The one-time programmable device can only be programmed once, such that the designated data block being stored is fully protected.

Abstract: An integrity check method applied to an electronic device includes: fetching at least one portion of external data into a specific memory, where the external data is stored within the electronic device; during fetching the portion of the external data into the specific memory, checking whether the size of the fetched data in the specific memory reaches a predetermined value, where the predetermined value is less than the total size of the external data; and when the size of the fetched data in the specific memory reaches the predetermined value, enabling an integrity check of the fetched data.

Abstract: A modulation method for symbols in a frame of a compact disc includes the steps of receiving a plurality of data words, modulating each data word into a code word of a corresponding data symbol, and providing a plurality of combinations of potential merge bits to be inserted between successive symbols of the frame. At least one combination of candidate merge bits is generated according to the plurality of combinations of potential merge bits, a data symbol immediately preceding the location of the candidate merge bits, and a data symbol immediately succeeding the location of the candidate merge bits. The combination of candidate merge bits which minimizes (optimizes) the absolute cumulative DSV is selected when a subsequent group of possible combinations of candidate merge bits is detected or after a predetermined delay, and the selected combination of candidate merge bits is inserted between the two successive data symbols.

Abstract: A modulation system includes an encoder for transferring data words to tentative code words. A DSV control bit generator determines the value of a DSV control bit according to the data words or the tentative code words to optimize the cumulative DSVs corresponding tentative code words, wherein the DSV control bit generator determines the value of a current DSV control bit when at least a subsequent DSV control bit is detected. A final code word generator generates final code words according to the determined DSV control bit and the tentative code words.

Abstract: An optical storage medium recording apparatus is provided a data preparing and ECC encoding circuit that both prepares the data by combining different categories of data into data sequences in accordance with a data layout on the optical storage medium and encodes the combined data. The encoded data is temporarily stored in a data buffer, and subsequently successively read out by a recording circuit for recording onto the optical storage medium according to the data layout. For a Blu-ray disc recording apparatus, the data preparing and ECC encoding circuit includes a LDC/BIS encoder for generating long distance error correction codes (LDC) and burst indicator subcodes (BIS) from the combined data to form LDC and BIS encoded data, which is temporarily stored in the data buffer. The recording circuit includes an interleave circuit for interleaving the LDC and BIS data to form physical clusters for recording on the disc.

Abstract: A method for securing firmware in a memory is provided. Memory data in the memory is checked. If the memory data in the memory meets a criterion, a host is allowed to read and write the entire memory. If not, the host is prevented from reading the entire memory.

Abstract: An embedded system and an operating method thereof are disclosed. The embedded system comprises a micro-processor and a co-processor. The co-processor can only process non-interruptible instructions. The micro-processor is powered by an operating system to control the embedded system. When a task requires execution, the micro-processor appoints the co-processor to execute at least one batch command block. The batch command block is compiled with a sequence of non-interruptible instructions. When the task is complete, the co-processor outputs a response signal to the micro-processor.

Abstract: A modulation method for a first data string having a plurality of symbols is disclosed. The method includes: appending a data string to the first data string to form a second data string; and converting the second data string to a code word sequence by converting each of the symbols in the first data string to a code word according to predetermined modulation rules and a symbol set selected from the second data string. Each code word has a first fixed number of bits, each symbol has a second fixed number of bits, and each symbol set has a fixed number of symbols.

Abstract: A modulation method for symbols in a frame of a compact disc includes the steps of receiving a plurality of data words, modulating each data word into a code word of a corresponding data symbol, and providing a plurality of combinations of potential merge bits to be inserted between successive symbols of the frame. At least one combination of candidate merge bits is generated according to the plurality of combinations of potential merge bits, a data symbol immediately preceding the location of the candidate merge bits, and a data symbol immediately succeeding the location of the candidate merge bits. The combination of candidate merge bits which minimizes (optimizes) the absolute cumulative DSV is selected when a subsequent group of possible combinations of candidate merge bits is detected or after a predetermined delay, and the selected combination of candidate merge bits is inserted between the two successive data symbols.

Abstract: A jitter measuring method and device, which is capable of measuring jitters in serial digital signal without high-frequency reference clock. The jitter measuring device comprises a rough length measuring unit for measuring rough length for each pulse of the serial digital signal according to a reference clock, and a phase error measuring unit for measuring the phase errors between the edges of the reference clock and the serial digital signal by multi-phase clocks, which are generated by a multi-phase generator according to the reference clock. The jitter measuring device computes the precise length according to the rough length and the phase error, and measures the jitters from the precise length by filters.

Abstract: A jitter measuring method and device, which is capable of measuring jitters in serial digital signal without high-frequency reference clock. The jitter measuring device comprises a rough length measuring unit for measuring rough length for each pulse of the serial digital signal according to a reference clock, and a phase error measuring unit for measuring the phase errors between the edges of the reference clock and the serial digital signal by multi-phase clocks, which are generated by a multi-phase generator according to the reference clock. The jitter measuring device computes the precise length according to the rough length and the phase error, and measures the jitters from the precise length by filters.