Patents by Inventor Yang Chu

Yang Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250111828
    Abstract: Disclosed are a display substrate and a display apparatus, wherein the display substrate may include a base substrate including a display region and a non-display region, and a drive circuit layer disposed on the base substrate, the drive circuit layer includes a pixel drive circuit located in the display region and a gate drive circuit located in the non-display region; a boundary of the display region includes an arc-shaped boundary, a non-display region located on an outside of the arc-shaped boundary is referred to as a rounded corner region, and the rounded corner region includes a plurality of first regions and at least one second region; the gate drive circuit is configured to provide a drive signal to the pixel drive circuit, and is partially located within a first region, and the second region is located between adjacent first regions.
    Type: Application
    Filed: February 22, 2023
    Publication date: April 3, 2025
    Inventors: Xinxin WANG, Lu BAI, Yang ZHOU, Song LIU, Yi QU, Zhiwen CHU, Lei HE, Peng XU
  • Publication number: 20250113586
    Abstract: An integrated circuit structure comprises a fin extending from a substrate, the fin comprising source and drain regions, and a channel region between the source and drain regions. A multilayer high-k gate stack comprising a plurality of materials extends conformally over the fin over the channel region. A gate electrode is over and on a topmost material in the multilayer high-k gate stack. Fluorine is implanted in the substrate beneath the multilayer high-k gate stack or in the plurality of materials comprising the multilayer high-k gate stack.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Inventors: Rahul PANDEY, Yang CAO, Rahul RAMAMURTHY, Jubin NATHAWAT, Michael L. HATTENDORF, Jae HUR, Anant H. JAHAGIRDAR, Steven R. NOVAK, Tao CHU, Yanbin LUO, Minwoo JANG, Paul A. PACKAN, Owen Y. LOH, David J. TOWNER
  • Publication number: 20250113595
    Abstract: Multiple voltage threshold integrated circuit structures with local layout effect tuning, and methods of fabricating multiple voltage threshold integrated circuit structures with local layout effect tuning, are described. For example, an integrated circuit structure includes a first fin structure or vertical arrangement of horizontal nanowires. A second fin structure or vertical arrangement of horizontal nanowires is laterally spaced apart from the first fin structure or vertical arrangement of horizontal nanowires. An N-type gate structure is over the first fin structure or vertical arrangement of horizontal nanowires. A P-type gate structure is over the second fin structure or vertical arrangement of horizontal nanowires, the P-type gate structure in contact with the N-type gate structure with a PN boundary between the P-type gate structure and the N-type gate structure.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Inventors: Tao CHU, Minwoo JANG, Yanbin LUO, Paul PACKAN, Guowei XU, Chiao-Ti HUANG, Robin CHAO, Feng ZHANG, Ting-Hsiang HUNG, Chia-Ching LIN, Yang ZHANG, Chung-Hsun LIN, Anand S. MURTHY
  • Publication number: 20250113547
    Abstract: Integrated circuit structures having internal spacers for 2D channel materials, and methods of fabricating integrated circuit structures having internal spacers for 2D channel materials, are described. For example, an integrated circuit structure includes a stack of two-dimensional (2D) material nanowires. A gate structure is vertically around the stack of 2D material nanowires. Internal gate spacers are between vertically adjacent ones of the stack of 2D material nanowires and laterally adjacent to the gate structure. The 2D material nanowires are recessed relative to the internal gate spacers. Conductive contact structures are at corresponding ends of the stack of 2D material nanowires, the conductive contact structures adjacent to the internal gate spacers and vertically overlapping with the internal gate spacers.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Inventors: Chia-Ching LIN, Tao CHU, Chiao-Ti HUANG, Guowei XU, Robin CHAO, Feng ZHANG, Yue ZHONG, Yang ZHANG, Ting-Hsiang HUNG, Kevin P. O’BRIEN, Uygar E. AVCI, Carl H. NAYLOR, Mahmut Sami KAVRIK, Andrey VYATSKIKH, Rachel STEINHARDT, Chelsey DOROW, Kirby MAXEY
  • Publication number: 20250112120
    Abstract: Integrated circuit structures having deep via bar width tuning are described. For example, an integrated circuit structure includes a plurality of gate lines extending over first and second semiconductor nanowire stack channel structures or fin structures. A plurality of trench contacts is intervening with the plurality of gate lines. A conductive structure is between the first and second semiconductor nanowire stack channel structures or fin structures, the conductive structure having a first width in a first region and a second width in a second region between the first and second semiconductor nanowire stack channel structures or fin structures, the second width different than the first width.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Inventors: Tao CHU, Minwoo JANG, Yanbin LUO, Paul PACKAN, Conor P. PULS, Guowei XU, Chiao-Ti HUANG, Robin CHAO, Feng ZHANG, Ting-Hsiang HUNG, Chia-Ching LIN, Yang ZHANG, Chung-Hsun LIN, Anand S. MURTHY
  • Publication number: 20250113559
    Abstract: Trench contact structures with etch stop layers, and methods of fabricating trench contact structures with etch-stop layers, are described. In an example, an integrated circuit structure includes a fin structure. An epitaxial source or drain structure is on the fin structure. An isolation structure is laterally adjacent to sides of the fin structure. A dielectric layer is on at least a portion of a top surface of the isolation structure and partially surrounds the epitaxial source or drain structure and leaves an exposed portion of the epitaxial source or drain structure. A conductive trench contact structure is on the exposed portion of the epitaxial source or drain structure. The conductive trench contact structure does not extend into the isolation structure.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Inventors: Guowei XU, Chiao-Ti HUANG, Feng ZHANG, Robin CHAO, Tao CHU, Anand S. MURTHY, Ting-Hsiang HUNG, Chung-Hsun LIN, Oleg GOLONZKA, Yang ZHANG, Chia-Ching LIN
  • Publication number: 20250107175
    Abstract: Integrated circuit structures having reduced local layout effects, and methods of fabricating integrated circuit structures having reduced local layout effects, are described. For example, an integrated circuit structure includes an NMOS region including a first plurality of fin structures or vertical stacks of horizontal nanowires, and first alternating gate lines and trench contact structures over the first plurality of fin structures or vertical stacks of horizontal nanowires. The integrated circuit structure also includes a PMOS region including a second plurality of fin structures or vertical stacks of horizontal nanowires, and second alternating gate and trench contact structures over the second plurality of fin structures or vertical stacks of horizontal nanowires. A gate line is shared between the NMOS region and the PMOS region, and a trench contact structure is shared between the NMOS region and the PMOS region.
    Type: Application
    Filed: September 25, 2023
    Publication date: March 27, 2025
    Inventors: Tao CHU, Minwoo JANG, Yanbin LUO, Paul PACKAN, Guowei XU, Chiao-Ti HUANG, Robin CHAO, Feng ZHANG, Ting-Hsiang HUNG, Chia-Ching LIN, Yang ZHANG, Chung-Hsun LIN, Anand S. MURTHY
  • Publication number: 20250107156
    Abstract: Techniques are provided herein to form an integrated circuit having dielectric material formed in cavities beneath source or drain regions. The cavities may be formed within subfin portions of semiconductor devices. In one such example, a FET (field effect transistor) includes a gate structure extending around a fin or any number of nanowires of semiconductor material. The semiconductor material may extend in a first direction between source and drain regions while the gate structure extends over the semiconductor material in a second direction substantially orthogonal to the first direction. A dielectric fill may be formed in a recess beneath the source or drain regions, or a dielectric liner may be formed on sidewalls of the recess, to prevent epitaxial growth of the source or drain regions from the subfins. Removal of the semiconductor subfin from the backside may then be performed without causing damage to the source or drain regions.
    Type: Application
    Filed: September 21, 2023
    Publication date: March 27, 2025
    Applicant: Intel Corporation
    Inventors: Chiao-Ti Huang, Robin Chao, Jaladhi Mehta, Tao Chu, Guowei Xu, Ting-Hsiang Hung, Feng Zhang, Yang Zhang, Chia-Ching Lin, Chung-Hsun Lin, Anand Murthy
  • Publication number: 20250107212
    Abstract: Techniques are provided to form an integrated circuit having an airgap spacer between at least a transistor gate structure and an adjacent source or drain contact. In one such example, a FET (field effect transistor) includes a gate structure that extends around a fin or any number of nanowires (or nanoribbons or nanosheets, as the case may be) of semiconductor material. The semiconductor material may extend in a first direction between source and drain regions while the gate structure extends over the semiconductor material in a second direction. Airgaps are provided in the regions between the gate structures and the adjacent source/drain contacts. The airgaps have a low dielectric constant (e.g., around 1.0) to reduce the parasitic capacitance between the conductive structures.
    Type: Application
    Filed: September 21, 2023
    Publication date: March 27, 2025
    Applicant: Intel Corporation
    Inventors: Yang Zhang, Guowei Xu, Tao Chu, Robin Chao, Chiao-Ti Huang, Feng Zhang, Ting-Hsiang Hung, Chia-Ching Lin, Anand Murthy
  • Patent number: 12261226
    Abstract: A transistor device includes a channel region, a first source/drain region adjacent to a first end of the channel region and a second source/drain region adjacent to a second end of the channel region, a gate structure disposed on the channel region, the first source/drain region and the second source/drain region, and an interlayer dielectric (ILD) structure disposed on the gate structure. The ILD structure includes a first dielectric layer including a first set of sublayers. The first set of sublayers includes a first sublayer including a first dielectric material having a first hydrogen concentration and a second sublayer including the first dielectric material having a second hydrogen concentration lower than the first hydrogen concentration. The ILD structure further includes a second dielectric layer including a second set of sublayers. The second set of sublayers includes a third sublayer including a second dielectric material different from the first dielectric material.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: March 25, 2025
    Assignee: Applied Materials, Inc.
    Inventors: Yun-Chu Tsai, Dejiu Fan, Jung Bae Kim, Yang Ho Bae, Rodney Shunleong Lim, Dong Kil Yim
  • Patent number: 12259111
    Abstract: An electronic device with light-indicating function is provided. The electronic device includes a substrate, a first light source, a second light source, and a light guiding element. The substrate includes a first surface and a second surface, wherein the first surface is opposite to the second surface. The first light source is disposed on the first surface of the substrate, wherein the first light source faces the first direction, and the first light source provides a first light beam. The second light source is disposed on the first surface of the substrate, wherein the second light source faces the second direction, the second light source provides a second light beam, and the first direction is not parallel to the second direction. The light guiding element includes a first section and a second section.
    Type: Grant
    Filed: March 7, 2024
    Date of Patent: March 25, 2025
    Assignee: WISTRON NEWEB CORP.
    Inventors: Ching-Hsun Meng, Wei-Hung Liao, Yang-Chieh Ma, Hsueh-Chu Lin
  • Publication number: 20250098260
    Abstract: Integrated circuit structures having patch spacers, and methods of fabricating integrated circuit structures having patch spacers, are described. For example, an integrated circuit structure includes a stack of horizontal nanowires. A gate structure is vertically around the stack of horizontal nanowires, the stack of horizontal nanowires extending laterally beyond the gate structure. An internal gate spacer is between vertically adjacent ones of the stack of horizontal nanowires and laterally adjacent to the gate structure. An external gate spacer is along sides of the gate structure and over the stack of horizontal nanowires, the external gate spacer having one or more patch spacers therein.
    Type: Application
    Filed: September 19, 2023
    Publication date: March 20, 2025
    Inventors: Guowei XU, Feng ZHANG, Chiao-Ti HUANG, Robin CHAO, Tao CHU, Chung-Hsun LIN, Oleg GOLONZKA, Yang ZHANG, Ting-Hsiang HUNG, Chia-Ching LIN, Anand S. MURTHY
  • Publication number: 20250096114
    Abstract: Techniques to form semiconductor devices can include one or more via structures having substrate taps. A semiconductor device includes a gate structure around or otherwise on a semiconductor region (or channel region). The gate structure may extend over the semiconductor regions of any number of devices along a given direction. The gate structure may be interrupted, for example, between two transistors with a via structure that extends through an entire thickness of the gate structure and includes a conductive core. The via structure has a conductive foot portion beneath the gate structure and a conductive arm portion extending from the conductive foot portion along a height of the gate structure. The conductive foot portion has a greater width along the given direction than any part of the conductive arm portion. The via structure may further include one or more dielectric layers between the conductive arm portion and the gate structure.
    Type: Application
    Filed: September 19, 2023
    Publication date: March 20, 2025
    Applicant: Intel Corporation
    Inventors: Robin Chao, Chiao-Ti Huang, Guowei Xu, Ting-Hsiang Hung, Tao Chu, Feng Zhang, Chia-Ching Lin, Yang Zhang, Anand Murthy, Conor P. Puls
  • Patent number: 12256652
    Abstract: Some embodiments relate to an integrated circuit including one or more memory cells arranged over a semiconductor substrate between an upper metal interconnect layer and a lower metal interconnect layer. A memory cell includes a bottom electrode disposed over the lower metal interconnect layer, a data storage or dielectric layer disposed over the bottom electrode, and a top electrode disposed over the data storage or dielectric layer. An upper surface of the top electrode is in direct contact with the upper metal interconnect layer without a via or contact coupling the upper surface of the top electrode to the upper metal interconnect layer. Sidewall spacers are arranged along sidewalls of the top electrode, and have bottom surfaces that rest on an upper surface of the data storage or dielectric layer.
    Type: Grant
    Filed: February 16, 2024
    Date of Patent: March 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yang Chang, Wen-Ting Chu
  • Publication number: 20250087889
    Abstract: Embodiments of this application relate to the field of antennas, and provide a terminal antenna. The terminal antenna includes n radiators. The n radiators include a first radiator, a second radiator, and a third radiator. Lengths of the first radiator, the second radiator, and the third radiator form a descending arithmetic progression. The first radiator, the second radiator, and the third radiator are arranged in sequence to form two gaps. A coupling capacitance formed by the first radiator and the second radiator through the corresponding gap is greater than a coupling capacitance formed by the second radiator and the third radiator through the corresponding gap. The first radiator, the second radiator, and the third radiator are any three of the n radiators distributed in sequence.
    Type: Application
    Filed: April 28, 2023
    Publication date: March 13, 2025
    Inventors: Yiwu Hu, Kunpeng Wei, Shaojie Chu, Yang Lu
  • Publication number: 20250089310
    Abstract: Techniques are provided to form semiconductor devices that include through-gate structures (e.g., gate cut structures or conductive via structures) that have an airgap spacer between the structure and the adjacent gate electrode. In an example, a semiconductor device includes a gate structure around or otherwise on a semiconductor region (or channel region) that extends from a first source or drain region to a second source or drain region. A through-gate structure may extend in a third direction through an entire thickness of the gate structure and adjacent to the semiconductor region along the second direction. The through-gate structure may be a dielectric structure (e.g., a gate cut) or a conductive structure (e.g., a via). In either case, an airgap spacer exists between the through-gate structure and the gate structure.
    Type: Application
    Filed: September 13, 2023
    Publication date: March 13, 2025
    Applicant: Intel Corporation
    Inventors: Ting-Hsiang Hung, Yang Zhang, Robin Chao, Guowei Xu, Tao Chu, Chiao-Ti Huang, Feng Zhang, Chia-Ching Lin, Anand Murthy
  • Publication number: 20250087530
    Abstract: Techniques are provided to form semiconductor devices where portions of the gate structure (e.g., foot structures) adjacent to the subfins have been removed. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure includes a gate dielectric and a gate electrode. The gate structure may be interrupted, for example, between two transistors with a gate cut that extends through an entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. The gate cut includes dielectric lobe structures that extend outwards from the sidewalls of the gate cut. The lobe structures effectively replace foot structures of the gate structure between the gate cut and subfin portions of the semiconductor fins. Removing the gate foot structures contributes to the reduction of the parasitic capacitance in the semiconductor device.
    Type: Application
    Filed: September 8, 2023
    Publication date: March 13, 2025
    Applicant: Intel Corporation
    Inventors: Chiao-Ti Huang, Tao Chu, Guowei Xu, Robin Chao, Feng Zhang, Yang Zhang, Ting-Hsiang Hung, Anand Murthy
  • Publication number: 20250078699
    Abstract: A display panel includes a substrate, a plurality of display units (Px), at least one first data line, at least one second data line, at least one first detection control unit, at least one second detection control unit, at least one first detection line and at least one second detection line. The first detection line is located at least in a first bezel region, a first end of the first detection line is electrically connected with the first data line through a first detection control unit, and a second end is configured to receive a first detection signal. The second detection line is located at least in a bending region of a second bezel region, a first end of the second detection line is electrically connected to the second data line through a second detection control unit, and a second end is configured to receive the first detection signal.
    Type: Application
    Filed: August 31, 2022
    Publication date: March 6, 2025
    Inventors: Zhiwen CHU, Yi QU, Hongwei MA, Yi ZHANG, Yang ZHOU, Lu BAI, Aoyuan FENG
  • Publication number: 20250063589
    Abstract: Scheduling with split symbols for beam management is described. An apparatus is configured to receive, from a network node, DL signaling including a symbol in a first slot, and to measure a first measurement of a first beam during a first time portion, and a second measurement of a second beam during a second different time portion, of the symbol. The apparatus is configured to communicate, with the network node, using the first or second beam based on at least one of the first measurement or the second measurement. Another apparatus is configured to provide, for a UE, DL signaling including a symbol in a first slot, and to communicate, with the UE, using the first or second beam based on a first and/or second measurement. The first and second measurements are of first and second beams during a first and second different time portions of the symbol, respectively.
    Type: Application
    Filed: August 18, 2023
    Publication date: February 20, 2025
    Inventors: Kang GAO, Yongle WU, Jun ZHU, Derrick Albert CHU, Vasanthan RAGHAVAN, Yong LI, Ruhua HE, Sumant Jayaraman IYER, Kang YANG, Shrenik PATEL, Raghu Narayan CHALLA
  • Patent number: 12232333
    Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: February 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chieh-Fei Chiu, Wen-Ting Chu, Yong-Shiuan Tsair, Yu-Wen Liao, Chih-Yang Chang, Chin-Chieh Yang