Abstract: Various embodiments of the present application are directed a memory layout for reduced line loading. In some embodiments, a memory device comprises an array of bit cells, a first conductive line, a second conductive line, and a plurality of conductive bridges. The first and second conductive lines may, for example, be source lines or some other conductive lines. The array of bit cells comprises a plurality of rows and a plurality of columns, and the plurality of columns comprise a first column and a second column. The first conductive line extends along the first column and is electrically coupled to bit cells in the first column. The second conductive line extends along the second column and is electrically coupled to bit cells in the second column. The conductive bridges extend from the first conductive line to the second conductive line and electrically couple the first and second conductive lines together.

Abstract: Methods for performing a pre-clean process to remove an oxide in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a shallow trench isolation region over a semiconductor substrate; forming a gate stack over the shallow trench isolation region; etching the shallow trench isolation region adjacent the gate stack using an anisotropic etching process; and after etching the shallow trench isolation region with the anisotropic etching process, etching the shallow trench isolation region with an isotropic etching process, process gases for the isotropic etching process including hydrogen fluoride and ammonia.

Abstract: A display substrate and a display apparatus. The display substrate includes an electrostatic discharge protection circuit, a power supply line, and at least one auxiliary electrode. The electrostatic discharge protection circuit includes multiple electrostatic discharge protection units, at least one of which extends along a first inclined direction, there is a first preset included angle between the first inclined direction and a first direction, the first direction is an extension direction of a scan signal line in the display region, the first preset included angle is greater than 0° and less than 90°; the first trace region includes the power supply line and at least one auxiliary electrode, an orthographic projection of the at least one auxiliary electrode on a display substrate plane is overlapped with that of the power supply line on the display substrate plane, the at least one auxiliary electrode is connected with the power supply line.

Abstract: A system may include an electronic display panel having pixels, where each pixel may emit light based on a respective programming signal. The system may include a memory storing a map. The processing circuitry may determine a function for each pixel from the map. The processing circuitry may determine a respective control signal based on the function and a target brightness level for each pixel to generate multiple control signals, where the respective control signal is used to generate the respective programming signal for each pixel. The processing circuitry may determine a scaling factor based at least in part on the first map and may scale at least a subset of the multiple control signals based at least in part on the scaling factor.

Abstract: A method of fabricating a fin-like field effect transistor (FinFET) device includes providing a semiconductor substrate having a region for forming p-type metal-oxide-semiconductor (PMOS) devices and a region for forming n-type metal-oxide-semiconductor (PMOS) devices, forming fin structures in both regions of the substrate separated by isolation features, first forming source/drain (S/D) features in the PMOS region, and subsequently forming S/D features in the NMOS region. First forming the PMOS S/D features and then forming the NMOS S/D features results in a greater extent of loss of isolation features in the PMOS region than in the NMOS region.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure extended above a substrate along a first direction, and a first gate structure formed over the first fin structure along a second direction. The semiconductor device structure includes a first source/drain (S/D) structure formed over the first fin structure and adjacent to the first gate structure, and a cap layer formed on and in direct contact with the first S/D structure. The semiconductor device structure includes an isolation structure adjacent to the first gate structure and the first S/D structure along the first direction. The isolation structure extends from the first gate structure to the first S/D structure, and the first S/D structure has a protruding portion toward to the isolation structure, and the protruding portion of the first S/D structure is separated from the isolation structure by the cap layer.

Abstract: The present disclosure relates to an anti-fatigue Lactobacillus composition. The anti-fatigue Lactobacillus composition, which includes at least one of Lactobacillus brevis GKEX, Lactobacillus plantarum GKK1 and Lactobacillus johnsonii GKJ2 as an active ingredient, administered to a healthy subject for a continuous period of time, can significantly improve fatigue-related biochemical indices and prolong aerobic exercise time to exhaustion, and thus can be used as an active ingredient for preparation of various compositions for anti-fatigue and/or improving athletic ability.

Abstract: A galactose rapid quantitative detection system utilizing a test strip containing a concentration of galactose dehydrogenase as the enzyme and a concentration of trehalose as the stabilizer. The system includes a galactose solution composition including a galactose, a buffer and an antioxidant; a test strip, including an enzyme, and a stabilizer; and a meter. The meter includes a power supply unit for providing a signal; a connector for receiving the signal transmitting the signal to the test strip, the signal reacting with the electrochemical information, and the connector transmits the response signal to the meter; a calculation unit for calculating the response signal; an A/D convertor for receiving the response signal from the calculation unit, transforming the response signal into a digital reaction signal; a processor for processing the digital reaction signal; a display for displaying the digital reaction signal; and a digital terminal for receiving the digital reaction signal.

Abstract: A planar transparent antenna structure is provided. The planar transparent antenna structure includes a dielectric substrate, a radiation conductive layer and a ground conductive layer. The dielectric substrate has a first surface and a second surface. The radiation conductive layer is disposed on the first surface of the dielectric substrate. The ground conductive layer is disposed on the second surface of the dielectric substrate. The radiation conductive layer and the ground conductive layer are composed of a plurality of wires connected in a mesh manner. Each of the wires is composed of a plurality of grid lines connected in a mesh manner.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a stack of channel structures and a first epitaxial structure and a second epitaxial structure adjacent to opposite sides of the channel structures. The semiconductor device structure also includes a gate stack wrapped around the channel structures and a backside conductive contact connected to the second epitaxial structure. The second epitaxial structure is between a top of the backside conductive contact and a top of the gate stack. The semiconductor device structure further includes an etch stop layer extending along a sidewall of the backside conductive contact and a bottom of the gate stack.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method of manufacture comprises receiving a substrate including a semiconductor material stack formed thereon, wherein the semiconductor material stack includes a first semiconductor layer of a first semiconductor material and second semiconductor layer of a second semiconductor material that is different than the first semiconductor material. Patterning the semiconductor material stack to form a trench. The patterning includes performing a first etch process with a first etchant for a first duration and then performing a second etch process with a second etchant for a second duration, where the second etchant is different from the first etchant and the second duration is greater than the first duration. The first etch process and the second etch process are repeated a number of times. Then epitaxially growing a third semiconductor layer of the first semiconductor material on a sidewall of the trench.

Abstract: An electronic device with light-indicating function is provided. The electronic device includes a substrate, a first light source, a second light source, and a light guiding element. The substrate includes a first surface and a second surface, wherein the first surface is opposite to the second surface. The first light source is disposed on the first surface of the substrate, wherein the first light source faces the first direction, and the first light source provides a first light beam. The second light source is disposed on the first surface of the substrate, wherein the second light source faces the second direction, the second light source provides a second light beam, and the first direction is not parallel to the second direction. The light guiding element includes a first section and a second section.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure extended above a substrate along a first direction, and a first gate structure formed over the first fin structure along a second direction. The semiconductor device structure includes a first source/drain (S/D) structure formed over the first fin structure and adjacent to the first gate structure, and a cap layer formed on and in direct contact with the first S/D structure. The semiconductor device structure includes an isolation structure formed adjacent to the first gate structure and the first S/D structure along the first direction, and a bottom surface of the isolation structure is lower than a bottom surface of the first gate structure and a bottom surface of the first S/D structure.

Abstract: An IC device may have layout with reduced N-P boundary effect. The IC device may include two rows of transistors. The first row may include one or more P-type transistors. The second row may include N-type transistors. The gate electrode of a P-type transistor may include different conductive materials from the gate electrode of a N-type transistor. Each P-type transistor in the first row may be over a N-type transistor in the second row and contact the N-type transistor in the second row. For instance, the gate of the P-type transistor may contact the gate of the N-type transistor. Vacancy diffusion may occur at the boundary of the P-type transistor and the N-type transistor, causing N-P boundary effect. At least one or more other N-type transistors in the second row do not contact any P-type transistor, which can mitigate the N-P boundary effect in the IC device.

Abstract: An IC device includes a backside FTI separating a first transistor from a second transistor. The FTI may be between a source region of the first transistor and a drain region of the second transistor. The source region of the first transistor and the drain region of the second transistor may be different portions of a semiconductor structure, e.g., a fin or nanoribbon. The IC device may also include a frontside metal layer. The semiconductor structure may have a first surface and a second surface opposing the first surface. The first surface of the semiconductor structure may be closer to the metal layer and larger than the second surface of the semiconductor structure. The FTI may have a first surface and a second surface opposing the first surface. The first surface of the FTI may be closer to the metal layer but smaller than the second surface of the FTI.

Abstract: A metal gate fabrication method for nanoribbon-based transistors and associated transistor arrangements, IC structures, and devices are disclosed. An example IC structure fabricated using metal gate fabrication method described herein may include a first stack of N-type nanoribbons, a second stack of P-type nanoribbons, a first gate region enclosing portions of the nanoribbons of the first stack and including an NWF material between adjacent nanoribbons of the first stack, and a second gate region enclosing portions of the nanoribbons of the second stack and including a PWF material between adjacent nanoribbons of the second stack, where the second gate region includes the PWF material at sidewalls of the nanoribbons of the second stack and further includes the NWF material so that the PWF material is between the sidewalls of the nanoribbons of the second stack and the NWF material.

Abstract: A method of fabricating a fin-like field effect transistor (FinFET) device includes providing a semiconductor substrate having a region for forming p-type metal-oxide-semiconductor (PMOS) devices and a region for forming n-type metal-oxide-semiconductor (PMOS) devices, forming fin structures in both regions of the substrate separated by isolation features, first forming source/drain (S/D) features in the PMOS region, and subsequently forming S/D features in the NMOS region. First forming the PMOS S/D features and then forming the NMOS S/D features results in a greater extent of loss of isolation features in the PMOS region than in the NMOS region.

Abstract: Integrated circuit structures having source or drain structures and germanium N-channels are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion, the upper fin portion including germanium. A gate stack is over the upper fin portion of the fin. A first source or drain structure includes an epitaxial structure embedded in the fin at a first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at a second side of the gate stack. Each epitaxial structure includes a first semiconductor layer in contact with the upper fin portion, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer comprises silicon, germanium and phosphorous, and the second semiconductor layer comprises silicon and phosphorous.

Abstract: A semiconductor device according to the present disclosure includes a gate-all-around (GAA) transistor in a first device area and a fin-type field effect transistor (FinFET) in a second device area. The GAA transistor includes a plurality of vertically stacked channel members and a first gate structure over and around the plurality of vertically stacked channel members. The FinFET includes a fin-shaped channel member and a second gate structure over the fin-shaped channel member. The fin-shaped channel member includes semiconductor layers interleaved by sacrificial layers.

Abstract: Provided is a multi-degree-of-freedom steerable catheter soft robotic system, including a steerable catheter; a control circuit connected to the steerable catheter through electrical connections and selectively applying power to control the steerable catheter; and a power supply unit connected to the control circuit. The system also includes a driving circuit for driving the steerable catheter and a shielding disposed around the steerable catheter and shielding for heat and electromagnetic (EM) radiations. The present disclosure includes self-sensing shape-shifting spring coil actuators and a shape-shifting memory polymer (SMP) actuator for steerable catheter applications. In addition, the present disclosure also provides an electroless silver plating process, a silver chemical plating process, a carbon nanotube (CNT) composite process and a pneumatic process.