Patents by Inventor Yang Ho Bae

Yang Ho Bae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10068930
    Abstract: A display device comprising a first electrode that comprises a first region, a second region, and a third region located between the first region and the second region; a first insulating film disposed on the first electrode; a second electrode that is disposed on the first insulating film and comprises a fourth region overlapping the third region; a second insulating film disposed on the second electrode; a contact hole formed through the second insulating film, the first contact hole exposing the first, second and fourth regions; and a third electrode that is disposed on the second insulating film to cover the first contact hole, and is connected to at least one of the first region and the second region exposed by the first contact hole and the fourth region exposed by the first contact hole.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: September 4, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sol Ip Jeong, Sung Hee Hong, Se Jin Kim, Joong Tae Kim, Yang Ho Bae, Kyung Suk Jung, Beom Hee Han
  • Patent number: 10007131
    Abstract: A method for repairing a display device including a defective pixel area where a failure has occurred includes irradiating a first laser beam to a first interface provided between a first layer and a second layer that contact each other corresponding to the defective pixel area to form a protrusion-depression surface in one or more surfaces of the first layer and the second layer that form the first interface; and irradiating a second laser beam to the protrusion-depression surfaces provided in one or more surfaces of the first and second layers to burn the protrusion-depression surface.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: June 26, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yang Ho Bae, In Cheol Song, Ji Hoon Shin
  • Publication number: 20170294450
    Abstract: A display device comprising a first electrode that comprises a first region, a second region, and a third region located between the first region and the second region; a first insulating film disposed on the first electrode; a second electrode that is disposed on the first insulating film and comprises a fourth region overlapping the third region; a second insulating film disposed on the second electrode; a contact hole formed through the second insulating film, the first contact hole exposing the first, second and fourth regions; and a third electrode that is disposed on the second insulating film to cover the first contact hole, and is connected to at least one of the first region and the second region exposed by the first contact hole and the fourth region exposed by the first contact hole.
    Type: Application
    Filed: February 10, 2017
    Publication date: October 12, 2017
    Inventors: Sol Ip JEONG, Sung Hee HONG, Se Jin KIM, Joong Tae KIM, Yang Ho BAE, Kyung Suk JUNG, Beom Hee HAN
  • Publication number: 20160349549
    Abstract: A method for repairing a display device including a defective pixel area where a failure has occurred includes irradiating a first laser beam to a first interface provided between a first layer and a second layer that contact each other corresponding to the defective pixel area to form a protrusion-depression surface in one or more surfaces of the first layer and the second layer that form the first interface; and irradiating a second laser beam to the protrusion-depression surfaces provided in one or more surfaces of the first and second layers to burn the protrusion-depression surface.
    Type: Application
    Filed: February 19, 2016
    Publication date: December 1, 2016
    Inventors: Yang Ho BAE, In Cheol SONG, Ji Hoon SHIN
  • Patent number: 9443881
    Abstract: A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: September 13, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jean-Ho Song, Shin-Il Choi, Sun-Young Hong, Shi-Yul Kim, Ki-Yeup Lee, Jae-Hyoung Youn, Sung-Ryul Kim, O-Sung Seo, Yang-Ho Bae, Jong-Hyun Choung, Dong-Ju Yang, Bong-Kyun Kim, Hwa-Yeul Oh, Pil-Soon Hong, Byeong-Beom Kim, Je-Hyeong Park, Yu-Gwang Jeong, Jong-In Kim, Nam-Seok Suh
  • Patent number: 9431426
    Abstract: The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: August 30, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Je Hun Lee, Yang Ho Bae, Beom-Seok Cho, Chang Oh Jeong
  • Publication number: 20150357349
    Abstract: The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).
    Type: Application
    Filed: August 17, 2015
    Publication date: December 10, 2015
    Inventors: Je Hun LEE, Yang Ho BAE, Beom-Seok CHO, Chang Oh JEONG
  • Patent number: 9111802
    Abstract: The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: August 18, 2015
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Je Hun Lee, Yang Ho Bae, Beom-Seok Cho, Chang Oh Jeong
  • Publication number: 20150053984
    Abstract: A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.
    Type: Application
    Filed: October 20, 2014
    Publication date: February 26, 2015
    Inventors: JEAN-HO SONG, Shin-Il Choi, Sun-Young Hong, Shi-Yul Kim, Ki-Yeup Lee, Jae-Hyoung Youn, Sung-Ryul Kim, O-Sung Seo, Yang-Ho Bae, Jong-Hyun Choung, Dong-Ju Yang, Bong-Kyun Kim, Hwa-Yeul Oh, Pil-Soon Hong, Byeong-Beom Kim, Je-Hyeong Park, Yu-Gwang Jeong, Jong-In Kim, Nam-Seok Suh
  • Patent number: 8865528
    Abstract: A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: October 21, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jean-Ho Song, Shin-Il Choi, Sun-Young Hong, Shi-Yul Kim, Ki-Yeup Lee, Jae-Hyoung Youn, Sung-Ryul Kim, O-Sung Seo, Yang-Ho Bae, Jong-Hyun Choung, Dong-Ju Yang, Bong-Kyun Kim, Hwa-Yeul Oh, Pil-Soon Hong, Byeong-Beom Kim, Je-Hyeong Park, Yu-Gwang Jeong, Jong-In Kim, Nam-Seok Suh
  • Patent number: 8823005
    Abstract: A thin-film transistor (TFT) and a method of manufacturing the same are disclosed herein. The TFT may include a gate electrode disposed on an insulating substrate, an insulating layer disposed on the insulating substrate and the gate electrode, an active layer pattern disposed on the insulating layer to overlap the gate electrode, a source electrode disposed on the insulating layer and at least part of which overlaps the active layer pattern, and a drain electrode which is separated from the source electrode and at least part of which overlaps the active layer pattern. A first ohmic contact layer pattern may be disposed between the active layer pattern and the source electrode and between the active layer pattern and the drain electrode. The first ohmic contact layer may have higher nitrogen content on its surface than in other portions of the first ohmic contact layer.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: September 2, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: O-Sung Seo, Seong-Hun Kim, Yang-Ho Bae, Jean-Ho Song
  • Patent number: 8759834
    Abstract: A display panel includes; a lower gate line, a lower data line disposed substantially perpendicular to the lower gate line, a thin film transistor (“TFT”) connected to the lower gate line and the lower data line, an insulating layer disposed on the lower gate line, the lower data line, and the TFT and having a plurality of trenches exposing the lower gate line and the lower data line, an upper gate line disposed in the trench on the lower gate line, an upper data line disposed in the trench on the lower data line, and a pixel electrode connected to the TFT.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: June 24, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Joo-Ae Youn, Yang-Ho Bae, Chang-Oh Jeong, Chong-Chul Chai, Pil-Sang Yun, Hong Long Ning, Byeong-Beom Kim
  • Publication number: 20140167054
    Abstract: The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).
    Type: Application
    Filed: January 27, 2014
    Publication date: June 19, 2014
    Applicant: SAMSUNG DISPLAY CO., LTD.
    Inventors: Je Hun LEE, Yang Ho BAE, Beom-Seok CHO, Chang Oh JEONG
  • Patent number: 8637869
    Abstract: The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: January 28, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Je Hun Lee, Yang Ho Bae, Beom-Seok Cho, Chang Oh Jeong
  • Publication number: 20130306973
    Abstract: A display panel includes; a lower gate line, a lower data line disposed substantially perpendicular to the lower gate line, a thin film transistor (“TFT”) connected to the lower gate line and the lower data line, an insulating layer disposed on the lower gate line, the lower data line, and the TFT and having a plurality of trenches exposing the lower gate line and the lower data line, an upper gate line disposed in the trench on the lower gate line, an upper data line disposed in the trench on the lower data line, and a pixel electrode connected to the TFT.
    Type: Application
    Filed: July 22, 2013
    Publication date: November 21, 2013
    Inventors: Joo-Ae YOUN, Yang-Ho BAE, Chang-Oh JEONG, Chong-Chul CHAI, Pil-Sang YUN, Honglong NING, Byeong-Beom KIM
  • Patent number: 8557621
    Abstract: A method for manufacturing a thin film transistor array panel, including: sequentially forming a first silicon layer, a second silicon layer, a lower metal layer, and an upper metal layer on a gate insulating layer and a gate line; forming a first film pattern on the upper metal layer; forming a first lower metal pattern and a first upper metal pattern that includes a protrusion, by etching the upper metal layer and the lower metal layer; forming first and second silicon patterns by etching the first and second silicon layers; forming a second film pattern by ashing the first film pattern; forming a second upper metal pattern by etching the first upper metal pattern; forming a data line and a thin film transistor by etching the first lower metal pattern and the first and second silicon patterns; and forming a passivation layer and a pixel electrode on the resultant.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: October 15, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jong-Hyun Choung, Yang Ho Bae, Jean Ho Song, O Sung Seo, Sun-Young Hong, Hwa Yeul Oh, Bong-Kyun Kim, Nam Seok Suh, Dong-Ju Yang, Wang Woo Lee
  • Patent number: 8492190
    Abstract: A method for manufacturing a display panel includes; formation of a lower gate line, disposal of a semiconductor on the lower gate line, disposal of a lower data line substantially perpendicular to the lower gate line, disposal of an insulating layer having a plurality of trenches exposing the lower gate line and the lower data line on the lower data line, disposal of an upper gate line directly on the lower gate line and within the plurality of trenches, and disposal of an upper data line directly on the lower data line and within the plurality of trenches.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: July 23, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Joo-Ae Youn, Yang-Ho Bae, Chang-Oh Jeong, Chong-Chul Chai, Pil-Sang Yun, Honglong Ning, Byeong-Beom Kim
  • Patent number: 8372701
    Abstract: The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).
    Type: Grant
    Filed: October 8, 2009
    Date of Patent: February 12, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Je-Hun Lee, Yang-Ho Bae, Beom-Seok Cho, Chang-Oh Jeong
  • Patent number: 8273612
    Abstract: In a display panel and a method of manufacturing the display panel, a gate line, a data line, and source and drain electrodes including a same material as the data line are formed on a substrate constituting the display panel, and the data line includes an aluminum based alloy containing sufficient nickel to inhibit corrosion during dry etching. The corrosion resistance of the AlNi-containing alloy helps prevent corrosion of the data line, the source electrode, and the drain electrode during selective dry etching that shapes these lines and electrodes.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: September 25, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Seok Oh, Yang-Ho Bae, Pil-Sang Yun, Byeong-Beom Kim, Seung-Ha Choi, Sang-Gab Kim, Chang-Ho Jeong, Shin-Il Choi, Hong-Kee Chin, Yu-Gwang Jeong, Dong-Ju Yang
  • Publication number: 20120228619
    Abstract: A display panel includes; a lower gate line, a lower data line disposed substantially perpendicular to the lower gate line, a thin film transistor (“TFT”) connected to the lower gate line and the lower data line, an insulating layer disposed on the lower gate line, the lower data line, and the TFT and having a plurality of trenches exposing the lower gate line and the lower data line, an upper gate line disposed in the trench on the lower gate line, an upper data line disposed in the trench on the lower data line, and a pixel electrode connected to the TFT.
    Type: Application
    Filed: May 16, 2012
    Publication date: September 13, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joo-Ae YOUN, Yang-Ho BAE, Chang-Oh JEONG, Chong-Chul CHAI, Pil-Sang YUN, Honglong NING, Byeong-Beom KIM