Abstract: A display panel includes; a lower gate line, a lower data line disposed substantially perpendicular to the lower gate line, a thin film transistor (“TFT”) connected to the lower gate line and the lower data line, an insulating layer disposed on the lower gate line, the lower data line, and the TFT and having a plurality of trenches exposing the lower gate line and the lower data line, an upper gate line disposed in the trench on the lower gate line, an upper data line disposed in the trench on the lower data line, and a pixel electrode connected to the TFT.

Abstract: A display panel includes; a lower gate line, a lower data line disposed substantially perpendicular to the lower gate line, a thin film transistor (“TFT”) connected to the lower gate line and the lower data line, an insulating layer disposed on the lower gate line, the lower data line, and the TFT and having a plurality of trenches exposing the lower gate line and the lower data line, an upper gate line disposed in the trench on the lower gate line, an upper data line disposed in the trench on the lower data line, and a pixel electrode connected to the TFT.

Abstract: A method for manufacturing a thin film transistor array panel, including: sequentially forming a first silicon layer, a second silicon layer, a lower metal layer, and an upper metal layer on a gate insulating layer and a gate line; forming a first film pattern on the upper metal layer; forming a first lower metal pattern and a first upper metal pattern that includes a protrusion, by etching the upper metal layer and the lower metal layer; forming first and second silicon patterns by etching the first and second silicon layers; forming a second film pattern by ashing the first film pattern; forming a second upper metal pattern by etching the first upper metal pattern; forming a data line and a thin film transistor by etching the first lower metal pattern and the first and second silicon patterns; and forming a passivation layer and a pixel electrode on the resultant.

Abstract: Provided are a wire structure, a method of forming a wire, a thin film transistor (TFT) substrate, and a method of manufacturing the TFT substrate. The wire structure includes a barrier layer disposed on a lower structure, a copper conductive layer comprising copper or copper alloy disposed on the barrier layer, an intermediate layer comprising copper nitride disposed on the copper conductive layer, and a capping layer disposed on the intermediate layer.

Abstract: Provided are a wire structure, a method for fabricating a wire, a thin film transistor (TFT) substrate, and a method for fabricating a TFT substrate.

Abstract: A thin-film transistor (TFT) and a method of manufacturing the same are disclosed herein. The TFT may include a gate electrode disposed on an insulating substrate, an insulating layer disposed on the insulating substrate and the gate electrode, an active layer pattern disposed on the insulating layer to overlap the gate electrode, a source electrode disposed on the insulating layer and at least part of which overlaps the active layer pattern, and a drain electrode which is separated from the source electrode and at least part of which overlaps the active layer pattern. A first ohmic contact layer pattern may be disposed between the active layer pattern and the source electrode and between the active layer pattern and the drain electrode. The first ohmic contact layer may have higher nitrogen content on its surface than in other portions of the first ohmic contact layer.

Abstract: A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.

Abstract: A display substrate includes an insulating substrate, a thin-film transistor (TFT), a pixel electrode, a signal line and a pad part. The insulating substrate has a display region and a peripheral region surrounding the display region. The TFT is in the display region of the insulating substrate. The pixel electrode is in the display region of the insulating substrate and electrically connected to the TFT. The signal line is on the insulating substrate and extends from the peripheral region toward the display region. The pad part is in the peripheral region and electrically connects to the signal line. The pad part is formed in a trench of the insulating substrate and includes a region that extends into the insulating substrate. Therefore, the signal line may be securely attached to the insulating substrate.

Abstract: A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.

Abstract: In a display panel and a method of manufacturing the display panel, a gate line, a data line, and source and drain electrodes including a same material as the data line are formed on a substrate constituting the display panel, and the data line includes an aluminum based alloy containing sufficient nickel to inhibit corrosion during dry etching. The corrosion resistance of the AlNi-containing alloy helps prevent corrosion of the data line, the source electrode, and the drain electrode during selective dry etching that shapes these lines and electrodes.

Abstract: Provided are a wire structure, a method for fabricating a wire, a thin film transistor (TFT) substrate, and a method for fabricating a TFT substrate.

Abstract: A thin film transistor showing desirable contact characteristics during contact with indium tin oxide (ITO) or indium zinc oxide (IZO), in which a first conductive pattern including a gate electrode and a second conductive pattern including a source electrode and a drain electrode are formed without an etching process, a TFT substrate including the TFTs, and a method of manufacturing the same. The thin film transistor includes a gate electrode formed of a first conductive layer, a gate insulating layer covering the gate electrode, a semiconductor layer forming a channel on the gate insulating layer; an ohmic contact layer formed on the semiconductor layer, and a source electrode and a drain electrode formed of a second conductive layer and of a third conductive layer. The second conductive layer includes an aluminum-nickel alloy and nitrogen and is formed on the semiconductor layer. The third conductive layer includes an aluminum-nickel alloy and is formed on the second conductive layer.

Abstract: Provided are a wire structure, a method for fabricating a wire, a thin film transistor (TFT) substrate, and a method for fabricating a TFT substrate. The wire structure includes a barrier layer formed on a substrate and including copper nitride and a copper conductive layer formed on the barrier layer and including copper or a copper alloy.

Abstract: A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.

Abstract: A thin film conductor having improved adhesion and superior conductivity, a method for fabricating the same, a thin film transistor (TFT) plate including the thin film conductor, and a method for fabricating the TFT plate are provided. The thin film conductor includes an adhesive layer containing an oxidation-reactive metal or silicidation-reactive metal and silver, a silver conductive layer formed on the adhesive layer, and a protection layer formed on the silver conductive layer and containing an oxidation-reactive metal and silver.

Abstract: The invention provides a thin film transistor (TFT) array panel that includes an insulating substrate; a gate line formed on the insulating substrate and having a first layer of an Al containing metal, a second layer of a Cu containing metal that is thicker than the first layer, and a gate electrode; a gate insulating layer arranged on the gate line; a semiconductor arranged on the gate insulating layer; a data line having a source electrode and arranged on the gate insulating layer and the semiconductor; a drain electrode arranged on the gate insulating layer and the semiconductor and facing the source electrode; a passivation layer having a contact hole and arranged on the data line and the drain electrode; and a pixel electrode arranged on the passivation layer and coupled with the drain electrode through the contact hole.

Abstract: A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.

Abstract: A TFT substrate includes a base substrate, a gate wiring formed on the base substrate, a gate insulation layer, an activation layer, an oxidation-blocking layer, a data wiring, a protection layer and a pixel electrode. The gate wiring includes a gate line and a gate electrode. The gate insulation layer is formed on the base substrate to cover the gate wiring. The activation layer is formed on the gate insulation layer. The oxidation-blocking layer is formed on the activation layer. The data wiring includes a data line, a source electrode and a drain electrode. The source and drain electrodes are disposed on the oxidation-blocking layer therefore lowering the on-current (“Ion”) for turning on the TFT and increasing the off-current (“Ioff”) for turning off the TFT due to the oxidation-blocking layer.

Abstract: The present invention provides a TFT array panel and a manufacturing method of the same, which has signal lines including a lower layer of an Al containing metal and an upper layer of a molybdenum alloy (Mo-alloy) comprising molybdenum (Mo) and at least one of niobium (Nb), vanadium (V), and titanium (Ti). Accordingly, undercut, overhang, and mouse bites which may arise in an etching process, are prevented, and TFT array panels that have signal lines having low resistivity and good contact characteristics are provided.

Abstract: A thin film transistor showing desirable contact characteristics during contact with indium tin oxide (ITO) or indium zinc oxide (IZO), in which a first conductive pattern including a gate electrode and a second conductive pattern including a source electrode and a drain electrode are formed without an etching process, a TFT substrate including the TFTs, and a method of manufacturing the same. The thin film transistor includes a gate electrode formed of a first conductive layer, a gate insulating layer covering the gate electrode, a semiconductor layer forming a channel on the gate insulating layer; an ohmic contact layer formed on the semiconductor layer, and a source electrode and a drain electrode formed of a second conductive layer and of a third conductive layer. The second conductive layer includes an aluminum-nickel alloy and nitrogen and is formed on the semiconductor layer. The third conductive layer includes an aluminum-nickel alloy and is formed on the second conductive layer.