Patents by Inventor Yang Pan

Yang Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods and compositions for treatment of COPD diseases
    Patent number: 10046004
    Abstract: The present disclosure relates to treatment of a pulmonary disease. The methods and kits provided herein facilitate relieving the symptoms resulting from the pulmonary disease (e.g., asthma, chronic obstructive pulmonary disease (COPD), etc.).
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: August 14, 2018
    Assignee: Shanghai KE Pharmaceutical Co., LTD
    Inventors: Minsheng Zhu, Jie Sun, Yang Pan
  • Selective self-aligned patterning of silicon germanium, germanium and type III/V materials using a sulfur-containing mask
    Patent number: 10043672
    Abstract: A method for patterning a substrate including multiple layers using a sulfur-based mask includes providing a substrate including a first layer and a second layer arranged on the first layer. The first layer includes a material selected from a group consisting of germanium, silicon germanium and type III/V materials. The method includes depositing a mask layer including sulfur species on sidewalls of the first layer and the second layer by exposing the substrate to a first wet chemistry. The method includes removing the mask layer on the sidewalls of the second layer while not completely removing the mask layer on the sidewalls of the first layer by exposing the substrate to a second wet chemistry. The method includes selectively etching the second layer relative to the first layer and the mask layer on the sidewalls of the first layer by exposing the substrate to a third wet chemistry.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: August 7, 2018
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Daniel Peter, Samantha Tan, Reza Arghavani, Yang Pan
  • Formation method of semiconductor device structure with semiconductor nanowire
    Patent number: 10043665
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate, a first source portion and a first drain portion over the substrate, and a first semiconductor nanowire over the substrate and between the first source portion and the first drain portion. The first semiconductor nanowire includes a first portion over the substrate and a second portion over the first portion, and the first portion has a first width, and the second portion has a second width, and the second width is less than the first width. The semiconductor device structure also includes a first gate structure over the second portion of the first semiconductor nanowire.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: August 7, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shahaji B. More, Zheng-Yang Pan, Cheng-Han Lee, Shih-Chieh Chang, Chandrashekhar Prakash Savant
  • Structure of semiconductor device with source/drain structures
    Patent number: 10026840
    Abstract: Structures of a semiconductor device are provided. The semiconductor device includes a substrate, a gate structure over the substrate, and a first recess and a second recess in the substrate and at opposite sides of the gate structure. The semiconductor device also includes two source/drain structures over the first recess and the second recess respectively. At least one of the source/drain structures includes a first doped region partially filling in the first recess, a second doped region over the first doped region, and a third doped region over the second doped region. The second doped region contains more dopants than the first doped region or the third doped region.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: July 17, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Zheng-Yang Pan, Chun-Chieh Wang, Cheng-Han Lee, Shih-Chieh Chang
  • Semiconductor Device and Method
    Publication number: 20180174913
    Abstract: A semiconductor device and method includes: forming a gate stack over a substrate; growing a source/drain region adjacent the gate stack, the source/drain region being n-type doped Si; growing a semiconductor cap layer over the source/drain region, the semiconductor cap layer having Ge impurities, the source/drain region free of the Ge impurities; depositing a metal layer over the semiconductor cap layer; annealing the metal layer and the semiconductor cap layer to form a silicide layer over the source/drain region, the silicide layer having the Ge impurities; and forming a metal contact electrically coupled to the silicide layer.
    Type: Application
    Filed: June 8, 2017
    Publication date: June 21, 2018
    Inventors: Shahaji B. More, Zheng-Yang Pan, Cheng-Han Lee, Shih-Chieh Chang
  • Distributed automatic level control for a microphone array
    Patent number: 9998825
    Abstract: A distributed automatic level control function is provided, in which information relating to a common automatic level control parameter is transmitted to each of a plurality of microphone devices, wherein the information transmitted to at least one microphone device is derived from an audio sample of at least one different microphone device. Each microphone device produces the common automatic level control parameter based on the information received by the microphone device and applies the common automatic level control parameter produced by the microphone device to a distributed automatic level controller of the microphone device.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: June 12, 2018
    Assignee: Invensense, Inc.
    Inventors: Dongqin Yan, Jie Fu, Yang Pan
  • FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE WITH SEMICONDUCTOR NANOWIRE
    Publication number: 20180151357
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate, a first source portion and a first drain portion over the substrate, and a first semiconductor nanowire over the substrate and between the first source portion and the first drain portion. The first semiconductor nanowire includes a first portion over the substrate and a second portion over the first portion, and the first portion has a first width, and the second portion has a second width, and the second width is less than the first width. The semiconductor device structure also includes a first gate structure over the second portion of the first semiconductor nanowire.
    Type: Application
    Filed: January 5, 2017
    Publication date: May 31, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shahaji B. MORE, Zheng-Yang PAN, Cheng-Han LEE, Shih-Chieh CHANG, Chandrashekhar Prakash SAVANT
  • Dopant Concentration Boost in Epitaxially Formed Material
    Publication number: 20180151730
    Abstract: A dopant boost in the source/drain regions of a semiconductor device, such as a transistor can be provided. A semiconductor device can include a doped epitaxy of a first material having a plurality of boosting layers embedded within. The boosting layers can be of a second material different from the first material. Another device can include a source/drain feature of a transistor. The source/drain feature includes a doped source/drain material and one or more embedded distinct boosting layers. A method includes growing a boosting layer in a recess of a substrate, where the boosting layer is substantially free of dopant. The method also includes growing a layer of doped epitaxy in the recess on the boosting layer.
    Type: Application
    Filed: January 27, 2017
    Publication date: May 31, 2018
    Inventors: Chih-Yu Ma, Zheng-Yang Pan, Shih-Chieh Chang, Cheng-Han Lee
  • ALE smoothness: in and outside semiconductor industry
    Patent number: 9984858
    Abstract: Methods of etching and smoothening films by exposing to a halogen-containing plasma and an inert plasma within a bias window in cycles are provided. Methods are suitable for etching and smoothening films of various materials in the semiconductor industry and are also applicable to applications in optics and other industries.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: May 29, 2018
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Keren Jacobs Kanarik, Samantha Tan, Thorsten Lill, Meihua Shen, Yang Pan, Jeffrey Marks, Richard Wise
  • FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE
    Publication number: 20180145076
    Abstract: A fin field effect transistor (FinFET) device structure and method for forming the same are provided. The FinFET device structure includes a fin structure extending above a substrate. The fin structure includes a channel region, a portion of the channel region is made of silicon germanium (SiGe), and the silicon germanium (SiGe) has a gradient germanium (Ge) concentration. The FinFET device structure includes a gate structure formed on the channel region of the fin structure.
    Type: Application
    Filed: November 18, 2016
    Publication date: May 24, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Chieh WANG, Zheng-Yang PAN, Shih-Chieh CHANG, Yi-Min HUANG, Shahaji B. MORE, Tsung-Lin LEE
  • Method for controlling an electronic device equipped with sensing components, and associated apparatus
    Patent number: 9977521
    Abstract: A method for controlling an electronic device and an associated apparatus are provided, where the electronic device includes a proximity sensor for performing proximity detection, and the method includes the steps of: determining whether a first condition is satisfied according to an application status; performing a proximity sensor threshold adjustment operation corresponding to the first condition when the first condition is satisfied, to obtain an adjusted proximity sensor threshold for the proximity sensor; and performing proximity detection by utilizing the proximity sensor according to the adjusted proximity sensor threshold. The step of determining whether the first condition is satisfied according to the application status may further include: when a specific application is running in the foreground or launched, determining that the first condition is satisfied.
    Type: Grant
    Filed: January 19, 2015
    Date of Patent: May 22, 2018
    Assignee: HTC Corporation
    Inventors: Ssu-Po Chin, Abhishek Saxena, Sheng-Yang Pan
  • FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE
    Publication number: 20180130802
    Abstract: A fin field effect transistor (FinFET) device structure and method for forming the same are provided. The FinFET device structure includes a fin structure extending above a substrate, and the fin structure has a first portion and a second portion below the first portion, and the first portion and the second portion are made of different materials. The FinFET device structure includes an isolation structure formed on the substrate, and an interface between the first portion and the second portion of the fin structure is above a top surface of the isolation structure. The FinFET device structure includes a liner layer formed on sidewalls of the second portion of the fin structure.
    Type: Application
    Filed: November 10, 2016
    Publication date: May 10, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Chieh WANG, Zheng-Yang PAN, Yi-Min HUANG, Shih-Chieh CHANG, Tsung-Lin LEE
  • DATA COMMUNICATION BASED ON FREQUENCY
    Publication number: 20180131543
    Abstract: Systems and techniques for communicating data as a function of frequency are presented. In an implementation, a system includes a microelectromechanical systems (MEMS) sensor, a digital signal processor and a frequency detection circuit. The digital signal processor is coupled to the MEMS sensor. The frequency detection circuit receives data encoded as a function of frequency from the digital signal processor via a clock communication channel.
    Type: Application
    Filed: July 9, 2015
    Publication date: May 10, 2018
    Inventors: Yuanjin LI, Yang PAN, Jia ZHAO, Dan LI, Hao DING
  • METHOD, VIRTUAL REALITY APPARATUS AND RECORDING MEDIUM FOR FAST MOVING IN VIRTUAL REALITY
    Publication number: 20180129277
    Abstract: A method, a virtual reality (VR) apparatus and a recording medium for fast moving in a virtual reality are provided. The method is applicable to a VR apparatus including a head-mounted display (HMD), a locator and a calculation device. In the method, the calculation device executes an application of the VR to display frames of the application on the HMD. Then, the calculation device detects a moving direction of a user wearing the HMD in a three-dimensional space by using the locator. Afterwards, the calculation device fast moves a field of view of the frames from a current location toward the moving direction.
    Type: Application
    Filed: November 4, 2016
    Publication date: May 10, 2018
    Applicant: HTC Corporation
    Inventor: Sheng-Yang Pan
  • STRUCTURE OF SEMICONDUCTOR DEVICE WITH SOURCE/DRAIN STRUCTURES
    Publication number: 20180108775
    Abstract: Structures of a semiconductor device are provided. The semiconductor device includes a substrate, a gate structure over the substrate, and a first recess and a second recess in the substrate and at opposite sides of the gate structure. The semiconductor device also includes two source/drain structures over the first recess and the second recess respectively. At least one of the source/drain structures includes a first doped region partially filling in the first recess, a second doped region over the first doped region, and a third doped region over the second doped region. The second doped region contains more dopants than the first doped region or the third doped region.
    Type: Application
    Filed: October 13, 2016
    Publication date: April 19, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shahaji B. MORE, Zheng-Yang PAN, Chun-Chieh WANG, Cheng-Han LEE, Shih-Chieh CHANG
  • SUBSTRATE PROCESSING APPARATUS
    Publication number: 20180108549
    Abstract: The disclosure provides a substrate processing apparatus. The substrate processing apparatus includes: an etching region and one or more aerosol absorption devices arranged outside a substrate inlet of the etching region. The aerosol absorption device includes one or more spraying pipes. The aerosol absorption device is capable of absorbing the aerosol of the etching solution from the etching region, thereby reducing the damage of the aerosol to the substrate processing components.
    Type: Application
    Filed: February 7, 2017
    Publication date: April 19, 2018
    Inventors: Xiaoning LIU, Shikai WANG, Dongseob KIM, Jun GENG, Zhen HU, Xuanqi LIANG, Feng ZHANG, Tengfei HUANG, Yang PAN, Zhongren JIANG
  • Interference cancellation for throat microphone
    Patent number: 9930445
    Abstract: A throat microphone may include one or more transducers that are in contact with the skin in the region of the larynx of person, and may provide a vibration signal to a processing unit. The vibration signal may also include energy and information relating to secondary physiological phenomena such as breathing and heartbeat, in addition to the desired sonic signal. The processing unit may utilize information relating to the secondary physiological phenomena to control a filter that outputs the desired sonic signal.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: March 27, 2018
    Assignee: INVENSENSE, INC.
    Inventors: Jia Zhao, Yang Pan, Yuanjin Li, Dan Li, Hao Ding
  • SYK INHIBITORS
    Publication number: 20180071302
    Abstract: The application provides methods of treating or reducing thrombocytopenia, leukopenia, anemia, or neutropenia in a patient in need thereof, comprising the step of administering an effective amount of a compound selected from Compounds 1-6, disclosed herein.
    Type: Application
    Filed: September 14, 2017
    Publication date: March 15, 2018
    Inventors: Esteban M. Abella, Julie A. Di Paolo, Kathleen S. Keegan, Antonio Mario Querido Marcondes, Yang Pan, Arati V. Rao
  • Method for detecting presence and location of defects in a substrate
    Patent number: 9917189
    Abstract: A method for detecting the presence and location of defects over a substrate is disclosed. In an embodiment, the method may include: forming a semiconductor material in a plurality of openings in a reference wafer using an epitaxial growth process; performing one or more measurements on the reference wafer to obtain a baseline signal; forming a plurality of gate stacks and stressor regions in a plurality of substrates; after forming the plurality of gate stacks, forming the semiconductor material in a plurality of openings in a batch wafer; performing the one or more measurements on the batch wafer to obtain a batch signal; comparing the batch signal to the baseline signal; and determining whether a defect in present in the plurality of substrates based on the comparison.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: March 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wei Hung, Chien-Feng Lin, Zheng-Yang Pan, Shu Kuan
  • Clock and data recovery circuit and method
    Patent number: 9906231
    Abstract: A clock and data recovery (CDR) circuit is provided, and includes a sampling circuit, an error sampler, a phase detect circuit, and a phase adjust circuit. The sampling circuit generates a data signal according to an input data and a first clock signal, and generates an edge signal according to the input data and a second clock signal. The error sampler compares the input data with a reference voltage according to the first clock signal to generate a control signal. The phase detect circuit receives the control signal and generates a corrective signal according to the data signal and the edge signal. When the values of the control signal and the data signal are different, the phase detect circuit stops transmitting the corrective signal. The phase adjust circuit generates and adjusts the first and the second clock signal according to the corrective signal.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: February 27, 2018
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Juh Kang, Yen-Chung Chen, Chen-Yang Pan