Patents by Inventor Yang Pan

Yang Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200083044
    Abstract: Tin oxide film on a semiconductor substrate is etched selectively in a presence of silicon (Si), carbon (C), or a carbon-containing material (e.g., photoresist) by exposing the substrate to a process gas comprising hydrogen (H2) and a hydrocarbon. The hydrocarbon significantly improves the etch selectivity. In some embodiments an apparatus for processing a semiconductor substrate includes a process chamber configured for housing the semiconductor substrate and a controller having program instructions on a non-transitory medium for causing selective etching of a tin oxide layer on a substrate in a presence of silicon, carbon, or a carbon-containing material by exposing the substrate to a plasma formed in a process gas that includes H2 and a hydrocarbon.
    Type: Application
    Filed: November 18, 2019
    Publication date: March 12, 2020
    Inventors: Jengyi Yu, Samantha S.H. Tan, Yu Jiang, Hui-Jung Wu, Richard Wise, Yang Pan, Nader Shamma, Boris Volosskiy
  • Patent number: 10546748
    Abstract: Tin oxide films are used as spacers and hardmasks in semiconductor device manufacturing. In one method, tin oxide layer is formed conformally over sidewalls and horizontal surfaces of protruding features on a substrate. A passivation layer is then formed over tin oxide on the sidewalls, and tin oxide is then removed from the horizontal surfaces of the protruding features without being removed at the sidewalls of the protruding features. The material of the protruding features is then removed while leaving the tin oxide that resided at the sidewalls of the protruding features, thereby forming tin oxide spacers. Hydrogen-based and chlorine-based dry etch chemistries are used to selectively etch tin oxide in a presence of a variety of materials. In another method a patterned tin oxide hardmask layer is formed on a substrate by forming a patterned layer over an unpatterned tin oxide and transferring the pattern to the tin oxide.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: January 28, 2020
    Assignee: Lam Research Corporation
    Inventors: Jengyi Yu, Samantha Tan, Yu Jiang, Hui-Jung Wu, Richard Wise, Yang Pan, Nader Shamma, Boris Volosskiy
  • Patent number: 10535736
    Abstract: The present disclosure describes an exemplary method to form p-type fully strained channel (PFSC) or an n-type fully strained channel (NFSC) that can mitigate epitaxial growth defects or structural deformations in the channel region due to processing. The exemplary method can include (i) two or more surface pre-clean treatment cycles with nitrogen trifluoride (NF3) and ammonia (NH3) plasma, followed by a thermal treatment; (ii) a prebake (anneal); and (iii) a silicon germanium epitaxial growth with a silicon seed layer, a silicon germanium seed layer, or a combination thereof.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shahaji B. More, Huai-Tei Yang, Zheng-Yang Pan, Shih-Chieh Chang, Chun-Chieh Wang, Cheng-Han Lee
  • Patent number: 10522358
    Abstract: A FinFET device and method of forming the same are disclosed. The method includes forming a gate dielectric layer and depositing a metal oxide layer over the gate dielectric layer. The method also includes annealing the gate dielectric layer and the metal oxide layer, causing ions to diffuse from the metal oxide layer to the gate dielectric layer to form a doped gate dielectric layer. The method also includes forming a work function layer over the doped gate dielectric layer, and forming a gate electrode over the work function layer.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Wang, Zheng-Yang Pan, Shih-Chieh Chang, Cheng-Han Lee, Huai-Tei Yang, Shahaji B. More
  • Patent number: 10490661
    Abstract: A dopant boost in the source/drain regions of a semiconductor device, such as a transistor can be provided. A semiconductor device can include a doped epitaxy of a first material having a plurality of boosting layers embedded within. The boosting layers can be of a second material different from the first material. Another device can include a source/drain feature of a transistor. The source/drain feature includes a doped source/drain material and one or more embedded distinct boosting layers. A method includes growing a boosting layer in a recess of a substrate, where the boosting layer is substantially free of dopant. The method also includes growing a layer of doped epitaxy in the recess on the boosting layer.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: November 26, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yu Ma, Zheng-Yang Pan, Shih-Chieh Chang, Cheng-Han Lee
  • Publication number: 20190334029
    Abstract: A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer.
    Type: Application
    Filed: July 8, 2019
    Publication date: October 31, 2019
    Inventors: Chih-Yu Ma, Zheng-Yang Pan, Shahaji B. More, Shih-Chieh Chang, Cheng-Han Lee
  • Publication number: 20190272034
    Abstract: A motion detection system, a motion detection method and a computer-readable recording medium thereof are provided. The motion detection system includes one or more haptic feedback devices and a motion sensor. The haptic feedback devices are equipped with one or more haptic feedback elements. The haptic feedback elements are configured to perform a haptic feedback. The haptic feedback elements are triggered to perform a haptic feedback according to a haptic feedback command. A detection value from the motion sensor is modified in response to the haptic feedback elements being triggered by the haptic feedback command. Accordingly, the precision for positioning the haptic feedback devices can be improved.
    Type: Application
    Filed: November 15, 2018
    Publication date: September 5, 2019
    Applicant: HTC Corporation
    Inventor: Sheng-Yang Pan
  • Publication number: 20190244864
    Abstract: A semiconductor device and method includes: forming a gate stack over a substrate; growing a source/drain region adjacent the gate stack, the source/drain region being n-type doped Si; growing a semiconductor cap layer over the source/drain region, the semiconductor cap layer having Ge impurities, the source/drain region free of the Ge impurities; depositing a metal layer over the semiconductor cap layer; annealing the metal layer and the semiconductor cap layer to form a silicide layer over the source/drain region, the silicide layer having the Ge impurities; and forming a metal contact electrically coupled to the silicide layer.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 8, 2019
    Inventors: Shahaji B. More, Zheng-Yang Pan, Cheng-Han Lee, Shih-Chieh Chang
  • Publication number: 20190244805
    Abstract: Methods of and apparatuses for processing substrates having carbon-containing material using atomic layer etch and selective deposition are provided. Methods involve exposing a carbon-containing material on a substrate to an oxidant and igniting a first plasma to modify a surface of the substrate and exposing the modified surface to a second plasma at a bias power to remove the modified surface. Methods also involve selectively depositing a second carbon-containing material onto the substrate using a precursor having a chemical formula of CxHy, where x and y are integers greater than or equal to 1. ALE and selective deposition may be performed without breaking vacuum.
    Type: Application
    Filed: March 21, 2019
    Publication date: August 8, 2019
    Inventors: Samantha Tan, Jengyi Yu, Richard Wise, Nader Shamma, Yang Pan
  • Publication number: 20190237341
    Abstract: Tin oxide films are used as mandrels in semiconductor device manufacturing. In one implementation the process starts by providing a substrate having a plurality of protruding tin oxide features (mandrels) residing on an exposed etch stop layer. Next, a conformal layer of spacer material is formed both on the horizontal surfaces and on the sidewalls of the mandrels. The spacer material is then removed from the horizontal surfaces exposing the tin oxide material of the mandrels, without fully removing the spacer material residing at the sidewalls of the mandrel (e.g., leaving at least 50%, such as at least 90% of initial height at the sidewall). Next, mandrels are selectively removed (e.g., using hydrogen-based etch chemistry), while leaving the spacer material that resided at the sidewalls of the mandrels. The resulting spacers can be used for patterning the etch stop layer and underlying layers.
    Type: Application
    Filed: January 29, 2019
    Publication date: August 1, 2019
    Inventors: Jengyi Yu, Samantha SiamHwa Tan, Seongjun Heo, Boris Volosskiy, Sivananda Krishnan Kanakasabapathy, Richard Wise, Yang Pan, Hui-Jung Wu
  • Patent number: 10347764
    Abstract: A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: July 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yu Ma, Zheng-Yang Pan, Shahaji B. More, Shih-Chieh Chang, Cheng-Han Lee
  • Patent number: 10304659
    Abstract: Methods of etching and smoothening films by exposing to a halogen-containing plasma and an inert plasma within a bias window in cycles are provided. Methods are suitable for etching and smoothening films of various materials in the semiconductor industry and are also applicable to applications in optics and other industries.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: May 28, 2019
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Keren Jacobs Kanarik, Samantha Tan, Thorsten Lill, Meihua Shen, Yang Pan, Jeffrey Marks, Richard Wise
  • Publication number: 20190157154
    Abstract: The present disclosure describes an exemplary fabrication method of a p-type fully strained channel that can suppress the formation of {111} facets during a silicon germanium epitaxial growth. The exemplary method includes the formation of silicon epitaxial layer on a top, carbon-doped region of an n-type region. A recess is formed in the silicon epitaxial layer via etching, where the recess exposes the top, carbon-doped region of the n-type region. A silicon seed layer is grown in the recess, and a silicon germanium layer is subsequently epitaxially grown on the silicon seed layer to fill the recess. The silicon seed layer can suppress the formation of growth defects such as, for example, {111} facets, during the silicon germanium epitaxial layer growth.
    Type: Application
    Filed: November 21, 2017
    Publication date: May 23, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Chieh Wang, Huai-Tei Yang, Zheng-Yang Pan, Shahaji B. More, Shih-Chieh Chang, Cheng-Han Lee
  • Publication number: 20190148552
    Abstract: A method for forming a semiconductor device is provided. The method includes forming a gate stack to partially cover a semiconductor structure. The method also includes forming a first semiconductor material over the semiconductor structure. The method further includes forming a second semiconductor material over the first semiconductor material. In addition, the method includes forming a third semiconductor material over the second semiconductor material. The first semiconductor material and the third semiconductor material together surround the second semiconductor material. The second semiconductor material has a greater dopant concentration than that of the first semiconductor material or that of the third semiconductor material.
    Type: Application
    Filed: December 24, 2018
    Publication date: May 16, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. MORE, Zheng-Yang PAN, Chun-Chieh WANG, Cheng-Han LEE, Shih-Chieh CHANG
  • Patent number: 10269646
    Abstract: A semiconductor device and method includes: forming a gate stack over a substrate; growing a source/drain region adjacent the gate stack, the source/drain region being n-type doped Si; growing a semiconductor cap layer over the source/drain region, the semiconductor cap layer having Ge impurities, the source/drain region free of the Ge impurities; depositing a metal layer over the semiconductor cap layer; annealing the metal layer and the semiconductor cap layer to form a silicide layer over the source/drain region, the silicide layer having the Ge impurities; and forming a metal contact electrically coupled to the silicide layer.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shahaji B. More, Zheng-Yang Pan, Cheng-Han Lee, Shih-Chieh Chang
  • Patent number: 10269566
    Abstract: Methods of and apparatuses for processing substrates having carbon-containing material using atomic layer deposition and selective deposition are provided. Methods involve exposing a carbon-containing material on a substrate to an oxidant and igniting a first plasma at a first bias power to modify a surface of the substrate and exposing the modified surface to an inert plasma at a second bias power to remove the modified surface. Methods also involve selectively depositing a second carbon-containing material onto the substrate. ALE and selective deposition may be performed without breaking vacuum.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: April 23, 2019
    Assignee: Lam Research Corporation
    Inventors: Samantha Tan, Jengyi Yu, Richard Wise, Nader Shamma, Yang Pan
  • Publication number: 20190108982
    Abstract: Methods and apparatus for performing high energy atomic layer etching are provided herein. Methods include providing a substrate having a material to be etched, exposing a surface of the material to a modification gas to modify the surface and form a modified surface, and exposing the modified surface to an energetic particle to preferentially remove the modified surface relative to an underlying unmodified surface where the energetic particle has an ion energy sufficient to overcome an average surface binding energy of the underlying unmodified surface. The energy of the energetic particle used is very high; in some cases, the power applied to a bias used when exposing the modified surface to the energetic particle is at least 150 eV.
    Type: Application
    Filed: October 1, 2018
    Publication date: April 11, 2019
    Inventors: Wenbing Yang, Samantha Tan, Tamal Mukherjee, Keren Jacobs Kanarik, Yang Pan
  • Publication number: 20190096997
    Abstract: The present disclosure describes an exemplary method to form p-type fully strained channel (PFSC) or an n-type fully strained channel (NFSC) that can mitigate epitaxial growth defects or structural deformations in the channel region due to processing. The exemplary method can include (i) two or more surface pre-clean treatment cycles with nitrogen trifluoride (NF3) and ammonia (NH3) plasma, followed by a thermal treatment; (ii) a prebake (anneal); and (iii) a silicon germanium epitaxial growth with a silicon seed layer, a silicon germanium seed layer, or a combination thereof.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 28, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shahaji B. MORE, Huai-Tei YANG, Zheng-Yang PAN, Shih-Chieh CHANG, Chun-Chieh WANG, Cheng-Han LEE
  • Patent number: 10225119
    Abstract: Systems and techniques for communicating data as a function of frequency are presented. In an implementation, a system includes a microelectromechanical systems (MEMS) sensor, a digital signal processor and a frequency detection circuit. The digital signal processor is coupled to the MEMS sensor. The frequency detection circuit receives data encoded as a function of frequency from the digital signal processor via a clock communication channel.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: March 5, 2019
    Assignee: INVENSENSE, INC.
    Inventors: Yuanjin Li, Yang Pan, Jia Zhao, Dan Li, Hao Ding
  • Publication number: 20190067011
    Abstract: A FinFET device and method of forming the same are disclosed. The method includes forming a gate dielectric layer and depositing a metal oxide layer over the gate dielectric layer. The method also includes annealing the gate dielectric layer and the metal oxide layer, causing ions to diffuse from the metal oxide layer to the gate dielectric layer to form a doped gate dielectric layer. The method also includes forming a work function layer over the doped gate dielectric layer, and forming a gate electrode over the work function layer.
    Type: Application
    Filed: April 27, 2018
    Publication date: February 28, 2019
    Inventors: Chun-Chieh Wang, Zheng-Yang Pan, Shih-Chieh Chang, Cheng-Han Lee, Huai-Tei Yang, Shahaji B. More