Abstract: A system is disclosed. The system may include a processor and a memory coupled to the processor. A storage device may also be coupled to the processor. The storage device may include a first interface and a second interface. The storage device may be configured to extend the memory. A mode switch may select a selected interface of the first interface and the second interface for a command issued by the processor.

Abstract: Provided is a method of database management including locating, with a recovery logic, a first metadata table using a beginning metadata table key, reading, by the recovery logic, the first metadata table, retrieving, with the recovery logic, a first next metadata table key of the first metadata table, locating, by the recovery logic, a second metadata table based on the first next metadata table key or based on a third next metadata table key of a third metadata table having a third metadata table range between a first metadata table range of the first metadata table and a second metadata table range of the second metadata table, reading, by the recovery logic, the second metadata table, determining, by the recovery logic, the second metadata table lacks valid keys in the second metadata table range, and making available, by the recovery logic, memory space associated with the second metadata table.

Abstract: A system is disclosed. The system may include a first device including a first processor, and a second device including a second processor, a memory, a first storage, and a second storage. The first storage may operate at a first speed, and the second storage may operate at a second speed that is slower than the first speed. The second device may be remote relative to the first device. The first device may load a metadata from a memory address in the memory of the second device. The first device may also access a data from the second device based at least in part on the metadata in the memory of the second device.

Abstract: A device may include an interconnect interface, a memory system including one or more first type memory devices to receive first data, one or more second type memory devices to receive second data, and an accelerator configured to perform an operation using the first data and the second data. The memory system may further include a cache configured to cache the second data for the one or more second type memory devices. A device may include an interconnect interface, a memory system coupled to the interconnect interface to receive data, an accelerator coupled to the memory system, and virtualization logic configured to partition one or more resources of the accelerator into one or more virtual accelerators, wherein a first one of the one or more virtual accelerators may be configured to perform a first operation on a first portion of the data.

Abstract: A system and method for machine learning. The system includes a GPU with a GPU memory, and a key value storage device connected to the GPU memory. The method includes, writing, by the GPU, a key value request to a key value request queue in a input-output region of the GPU memory, the key value request including a key. The method further includes reading, by the key value storage device, the key value request from the key value request queue, and writing, by the key value storage device, in response to the key value request, a value to the input-output region of the GPU memory, the value corresponding to the key of the key value request.

Abstract: A storage device includes a nonvolatile memory device and a storage controller. The storage controller includes a multi-protocol host interface circuit that receives a first-type request including a first logical address from an external host and transmits/receives data corresponding to the first-type request with the external host by a block unit. Additionally, the multi-protocol host interface circuit receives a second-type request including a first physical address from the external host and transmits/receives data corresponding to the second-type request with the external host by a unit smaller than the block unit. A mapping cache manager manages an address translation table cache, sends an address translation request including the first physical address to the external host, and receives a response including mapping information corresponding to the first physical address from the external host.

Abstract: A system is disclosed. The system may include a first device including a first processor, and a second device including a second processor, a memory, a first storage, and a second storage. The first storage may operate at a first speed, and the second storage may operate at a second speed that is slower than the first speed. The second device may be remote relative to the first device. The first device may load a metadata from a memory address in the memory of the second device. The first device may also access a data from the second device based at least in part on the metadata in the memory of the second device.

Abstract: A storage device may include a storage medium, a storage device controller coupled to the storage medium, a host interface coupled to the storage device controller, and an attachable module interface configured to connect an attachable compute module to the storage device controller. The attachable module interface may include a data interface, a side-band interface, and/or a power interface. The attachable module interface may include a connector configured to connect the attachable compute module to the storage device controller. The storage device may include an enclosure having an opening configured to enable the attachable compute module to be connected to the attachable module interface through the opening. The storage device controller may be configured to utilize one or more resources of the attachable compute module. The storage device controller may be configured to communicate with the attachable compute module through one or more command extensions of a storage protocol.

Abstract: A method and redundant array of independent disks (RAID) system are provided. An operation is received from an application at a file system (FS) of the RAID system. A memory mapping module of the RAID system receives at least an FS logical block address (LBA) in accordance with the operation. The memory mapping module creates a mapping from a virtual memory of the application to a RAID array in a system memory of the RAID system using at least the FS LBA.

Abstract: A content provider system includes: a repository to store a catalog of content; a storage device pool to load content from among the catalog of content from the repository into one or more storage devices of the storage device pool; a first hosted device communicably connected to the storage device pool, and to execute the content stored in the storage device pool to provide the content to a first user device; a second hosted device communicably connected to the storage device pool, and to execute the content stored in the storage device pool to provide the content to a second user device; and one or more processing circuits to identify an available storage device from among the one or more storage devices of the storage device pool for serving a requested content to a requesting device from among the first and second hosted devices.

Abstract: A system is disclosed. A first storage device may supporting a cache coherent interconnect protocol, the cache coherent interconnect protocol including a block level protocol and a byte level protocol. A second storage device may also support the cache coherent interconnect protocol. A redundant array of independent disks (RAID) circuit may communicate with the first storage device and the second storage device. The RAID circuit may apply a RAID level to the first storage device and the second storage device. The RAID circuit may be configured to receive a request using the byte level protocol and to access data on the first storage device.

Abstract: A system is disclosed. The system may include a processor that may issue a byte level protocol request including a byte address. The system may also include a first storage device and a second storage device. The first storage device and the second storage device may support a cache coherent interconnect protocol, the cache coherent interconnect protocol including a block level protocol and a byte level protocol. The first storage device and the second storage device are included in a redundant array of independent disks (RAID). The first storage device may include a first address range, and the second storage device may include a second address range. The second storage device may provide a RAID address range associated with the first address range and the second address range. A decoder associated with the second storage device may be configured to receive the request from the processor. The decoder may determine that the byte address in the RAID address range is associated with a target address range.

Abstract: A system may include a receiver to receive a task. The task may include a portion of an algorithm, and may include a task power level and a task precision. The system may also include a circuit including a circuit power level and a circuit precision. The system may include first software to identify the circuit, and second software to assign the task to the circuit to reduce total power. The circuit precision may be greater than the task precision.

Abstract: A system for handling faulty pages, including: a host processor; host memory connected to the host processor over a first memory interface; and an expandable memory pool connected to the host processor over a second memory interface different from the first memory interface, the host memory including instructions that, when executed by the host processor, cause the host processor to: detect an error in a target page of a first memory device of the expandable memory pool; generate an interrupt in response to detecting the error; store in a faulty page log, faulty page information corresponding to the target page of the first memory device; and change a status of the target page of the first memory device from a first state to a second state according to the faulty page log.

Abstract: A storage device is disclosed. The storage device may comprise storage for input encoded data. A controller may process read requests and write requests from a host computer on the data in the storage. An in-storage compute controller may receive a predicate from the host computer to be applied to the input encoded data. A transcoder may include an index mapper to map an input dictionary to an output dictionary, with one entry in the input dictionary mapped to an entry in the output dictionary, and another entry in the input dictionary mapped to a “don't care” entry in the output dictionary.

Abstract: A Solid State Drive (SSD) is disclosed. The SSD may include ports to receive requests from a host and to send requests to a second storage device. The SSD may include flash storage for data. An SSD controller may process the requests received from the host and generate the requests sent to the second storage device. The SSD may act as a cache for the second storage device.

Abstract: A content provider system includes: a repository to store a catalog of content; a storage device including at least a first port and a second port; a first hosted device connected to the first port over a first storage interface for access to the storage device, and to execute content stored in the storage device to provide the content to a first user device; a second hosted device connected to the second port over a second storage interface for access to the storage device, and to execute the content stored in the storage device to provide the content to a second user device; and one or more processing circuits to control access to the storage device from the first and second ports by the first and second hosted devices.

Abstract: A method for communicating with a device may include running, at a device, an operating system, communicating, using a first function of an interconnect, with the device, and communicating, using a second function of the interconnect, with the operating system. The operating system may include communication logic, and the communicating with the operating may include communicating with the communication logic. The communication logic may one or more terminal support drivers, and the communicating with the communication logic may include communicating with the one or more terminal support drivers using a terminal application. The terminal application may run on a host. The second function of the interconnect may be configured to operate with a controller. The communicating with the operating system may include communicating with the operating system based on a privilege information. The host may be a management controller.

Abstract: A storage device includes a nonvolatile memory device and a storage controller. The storage controller includes a multi-protocol host interface circuit that receives a first-type request including a first logical address from an external host and transmits/receives data corresponding to the first-type request with the external host by a block unit. Additionally, the multi-protocol host interface circuit receives a second-type request including a first physical address from the external host and transmits/receives data corresponding to the second-type request with the external host by a unit smaller than the block unit. A mapping cache manager manages an address translation table cache, sends an address translation request including the first physical address to the external host, and receives a response including mapping information corresponding to the first physical address from the external host.

Abstract: According to one general aspect, an apparatus may include a host interface circuit configured to receive offloading instructions from a host processing device, wherein the offloading instructions instruct the apparatus to compute an error correction code associated with a plurality of data elements. The apparatus may include a memory interface circuit configured to receive the plurality of data elements. The apparatus may include a plurality of memory buffer circuits configured to temporarily store the plurality of data elements. The apparatus may include a plurality of error code computation circuits configured to, at least in part, compute the error correction code without additional processing by the host processing device.