Abstract: Provided is a system storing data received from an application or file system in a non-volatile memory system of single-level cells and multi-level cells in accordance with one or more data characteristics. The non-volatile memory system includes a non-volatile memory cell array having a plurality of multi-level cells forming a MLC area and a plurality of single-level cells forming a SLC area, and an interface unit analyzing a characteristic of the write data and generating a corresponding data characteristic signal. A flash transition layer receives the data characteristic signal, and determines whether the write data should be stored in the MLC area or the SLC area based on whether or not the write data will be accessed by the file, or whether the address associated with the write data is frequently updated or not.

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

Abstract: Disclosed is a multi-channel flash memory system formed by flash memories having pages divided into sectors and accessed by corresponding channels. An interface device is configured to access the flash memories via the channels by a unit of at least one sector, wherein the interface device divides an address into a plurality of addresses of sector unit and controls the divided addresses so as to be jumped by a given size.

Abstract: A memory system and corresponding method of wear-leveling are provided, the system including a controller, a random access memory in signal communication with the controller, and another memory in signal communication with the controller, the other memory comprising a plurality of groups, each group comprising a plurality of first erase units or blocks and a plurality of second blocks, wherein the controller exchanges a first block from a group with a second block in response to at least one block erase count within the group; and the method including receiving a command having a logical address, converting the logical address into a logical block number, determining a group number for a group that includes the converted logical block number, and checking whether group information comprising block erase counts for the group is loaded into random access memory, and if not, loading the group information into random access memory.

Abstract: A system and method for memory mapping are provided, the system including a logical unit to physical unit map table, data unit groups in signal communication with the map table, and log unit groups, each associated with a corresponding one of the data unit groups, where updated data for any data unit within one of the data unit groups is stored in any log unit within the corresponding one of the log unit groups, and the method including receiving write data for a logical unit number from a host determining which of a plurality of data block groups comprises the logical unit number, and storing the write data in any unfilled log unit of a log block group corresponding to the determined data block group.

Abstract: An apparatus, memory device controller and method of controlling a memory device are provided. The example apparatus may include a bad block bitmap referencing unit configured to obtain bad block information from a bad block bitmap based on a given memory address, the given memory address being one of a logical memory address and a physical memory address corresponding to the logical memory address, the bad block information indicating whether a given memory block corresponding to the given memory address is a bad block and a memory mapping unit configured to obtain the physical memory address corresponding to the logical memory address, and configured to obtain a reserved physical memory address corresponding to the physical memory address if the bad block information indicates that the given memory block is a bad block. In an example, the apparatus may be embodied as a memory device controller including a flash translation layer (FTL).

Abstract: Provided is a system storing data received from an application or file system in a non-volatile memory system of single-level cells and multi-level cells in accordance with one or more data characteristics.

Abstract: A memory system is disclosed with a file system; a flash translation layer (FTL) receiving a logical address from the file system and translating it into a physical address, and a flash memory receiving the physical address. The FTL includes flag information and offset information, the flag information indicating page order for a memory block in the flash memory is a wrap-around order and the offset information defining a starting page for the memory block.

Abstract: A method for operating a memory system including a flash memory device having a plurality of memory blocks comprises determining whether a read error generated during a read operation of the flash memory device is caused by read disturbance and replacing a memory block which includes the read error, with a spare memory block if the read error is caused by read disturbance.

Abstract: Methods and apparatus are provided for bandwidth management within Automatically Switched Optical Networks. An Optical Connection Controller (OCC) provides threshold based load balancing using an upper and a lower threshold for each port of a network element, and once port usage exceeds the upper threshold no more connections are allowed through the port until the port usage falls below the lower threshold. The OCC also minimizes fragmentation of a port so as to reduce the probability of call rejection as a result of fragmentation. The OCC also maintains a database of shortest paths between a network element and each destination, so that connections can be re-established quickly through alternate paths in the event of failure of a link or node. The OCC also provides the entire network with notification of a fault, thereby enhancing CR-LDP fault notification messaging.

Abstract: A method for initializing and operating a flash memory file system and a computer-readable medium storing a program adapted to perform the method are disclosed. The method includes programming the flash memory file system in order to conceptually divide logical blocks into logical groups, and storing erasure data for one of the logical groups in a first region of a meta block. The method also includes loading erasure data for one logical group into an external memory device and mapping the logical blocks of the current logical group to the physical blocks in accordance with the erasure data loaded into the external memory device. The method also includes storing data of a data file in a data block of a flash memory device in accordance with the mapping of the logical blocks to the physical blocks.

Abstract: Methods and apparatus are provided for bandwidth management within Automatically Switched Optical Networks. An Optical Connection Controller (OCC) provides threshold based load balancing using an upper and a lower threshold for each port of a network element, and once port usage exceeds the upper threshold no more connections are allowed through the port until the port usage falls below the lower threshold. The OCC also minimizes fragmentation of a port so as to reduce the probability of call rejection as a result of fragmentation. The OCC also maintains a database of shortest paths between a network element and each destination, so that connections can be re-established quickly through alternate paths in the event of failure of a link or node. The OCC also provides the entire network with notification of a fault, thereby enhancing CR-LDP fault notification messaging.

Abstract: A fairness scheme is disclosed for managing data flow between nodes in a bi-directional ring network. A method in accordance with the invention controls the output bandwidth of nodes in a bi-directional ring network by: identifying a congested span comprising a head node having a congested downstream link, and a plurality of chain nodes contributing to the congestion in the downstream link: adjusting the output bandwidth of the head node as a function of the congestion in the downstream link; and adjusting the output bandwidth of the chain nodes as a function of the congestion in the downstream link.