Abstract: Trench contact structures with etch stop layers, and methods of fabricating trench contact structures with etch-stop layers, are described. In an example, an integrated circuit structure includes a fin structure. An epitaxial source or drain structure is on the fin structure. An isolation structure is laterally adjacent to sides of the fin structure. A dielectric layer is on at least a portion of a top surface of the isolation structure and partially surrounds the epitaxial source or drain structure and leaves an exposed portion of the epitaxial source or drain structure. A conductive trench contact structure is on the exposed portion of the epitaxial source or drain structure. The conductive trench contact structure does not extend into the isolation structure.

Abstract: Integrated circuit structures having internal spacers for 2D channel materials, and methods of fabricating integrated circuit structures having internal spacers for 2D channel materials, are described. For example, an integrated circuit structure includes a stack of two-dimensional (2D) material nanowires. A gate structure is vertically around the stack of 2D material nanowires. Internal gate spacers are between vertically adjacent ones of the stack of 2D material nanowires and laterally adjacent to the gate structure. The 2D material nanowires are recessed relative to the internal gate spacers. Conductive contact structures are at corresponding ends of the stack of 2D material nanowires, the conductive contact structures adjacent to the internal gate spacers and vertically overlapping with the internal gate spacers.

Abstract: Multiple voltage threshold integrated circuit structures with local layout effect tuning, and methods of fabricating multiple voltage threshold integrated circuit structures with local layout effect tuning, are described. For example, an integrated circuit structure includes a first fin structure or vertical arrangement of horizontal nanowires. A second fin structure or vertical arrangement of horizontal nanowires is laterally spaced apart from the first fin structure or vertical arrangement of horizontal nanowires. An N-type gate structure is over the first fin structure or vertical arrangement of horizontal nanowires. A P-type gate structure is over the second fin structure or vertical arrangement of horizontal nanowires, the P-type gate structure in contact with the N-type gate structure with a PN boundary between the P-type gate structure and the N-type gate structure.

Abstract: Systems, methods, and related technologies for classification are described. In certain aspects, a plurality of device classification methods with associated models are accessed. Each of the classification methods have an associated reliability level. The models of classification methods with a higher reliability level than other classifications methods are used to at least one of train or tune the models associated with lower reliability level.

Abstract: The present invention relates to the technical field of power generation of power systems, in particular to an offshore integrated power supply system based on clean energy. The integrated power supply system comprises a power generation unit for providing energy, an energy storage unit for storing energy, a load unit for consuming energy, an energy management system, and a fuel cell, wherein the power generation unit comprises a photovoltaic power generation system, a wind power generation system, and a tidal power generation system; the energy storage unit comprises hydrogen storage and a battery pack; and the energy management system connects the power generation unit, the load unit, and the energy storage unit, and allocates the surplus energy from the power generation unit to the hydrogen storage and the battery pack after satisfying the load unit.

Abstract: In some embodiments, a method receives a video including interlaced frames. Second fields for a second frame and the second fields for a third frame are analyzed to determine estimated second fields for the first frame in an image space. The method converts the first fields and the estimated second fields for the first frame into first features and second features, respectively, in a feature space. The estimated second features are determined for the estimated second fields for the first frame based on the first features for the first frame. Backward features from the second frame and forward features from the third frame are used to determine the estimated second features for the first frame. The method outputs a prediction for the estimated second fields for the first frame based on the estimated second features and generates a first frame with the first fields and estimated second fields.

Abstract: Techniques are provided herein to form an integrated circuit having dielectric material formed in cavities beneath source or drain regions. The cavities may be formed within subfin portions of semiconductor devices. In one such example, a FET (field effect transistor) includes a gate structure extending around a fin or any number of nanowires of semiconductor material. The semiconductor material may extend in a first direction between source and drain regions while the gate structure extends over the semiconductor material in a second direction substantially orthogonal to the first direction. A dielectric fill may be formed in a recess beneath the source or drain regions, or a dielectric liner may be formed on sidewalls of the recess, to prevent epitaxial growth of the source or drain regions from the subfins. Removal of the semiconductor subfin from the backside may then be performed without causing damage to the source or drain regions.

Abstract: Integrated circuit structures having reduced local layout effects, and methods of fabricating integrated circuit structures having reduced local layout effects, are described. For example, an integrated circuit structure includes an NMOS region including a first plurality of fin structures or vertical stacks of horizontal nanowires, and first alternating gate lines and trench contact structures over the first plurality of fin structures or vertical stacks of horizontal nanowires. The integrated circuit structure also includes a PMOS region including a second plurality of fin structures or vertical stacks of horizontal nanowires, and second alternating gate and trench contact structures over the second plurality of fin structures or vertical stacks of horizontal nanowires. A gate line is shared between the NMOS region and the PMOS region, and a trench contact structure is shared between the NMOS region and the PMOS region.

Abstract: Techniques are provided to form an integrated circuit having an airgap spacer between at least a transistor gate structure and an adjacent source or drain contact. In one such example, a FET (field effect transistor) includes a gate structure that extends around a fin or any number of nanowires (or nanoribbons or nanosheets, as the case may be) of semiconductor material. The semiconductor material may extend in a first direction between source and drain regions while the gate structure extends over the semiconductor material in a second direction. Airgaps are provided in the regions between the gate structures and the adjacent source/drain contacts. The airgaps have a low dielectric constant (e.g., around 1.0) to reduce the parasitic capacitance between the conductive structures.

Abstract: The present disclosure relates to a technical field of optical lenses, and discloses a camera optical lens. The camera optical lens includes seven lenses. An order of the seven lenses is sequentially from an object side to an image side, which is shown as follows: a first lens having a positive refractive power, a second lens having a negative refractive power, a third lens having a negative refractive power, a fourth lens having a positive refractive power, a fifth lens having a negative refractive power, a sixth lens having a positive refractive power, and a seventh lens having a negative refractive power. The camera optical lens provided by the present disclosure has excellent optical characteristics, and further has characteristics of large aperture, wide-angle, and ultra-thin, especially suitable for mobile phone camera lens assemblies and WEB camera lenses, which are composed of camera components having high pixels.

Abstract: A wireless communication method for use in a wireless terminal is disclosed. The wireless communication method comprises receiving, from the wireless network node, a second signal based on a quasi-co-location assumption of a first signal when at least one event occurs, wherein the first signal and the second signal overlap in at least one time unit.

Abstract: Embodiments presented provide for modeling of wireline runs for hydrocarbon recovery operations. In embodiments, a run duration of wireline activities is split into a winch duration and a pass duration, wherein the pass duration is calculated using a machine learning model.

Abstract: Integrated circuit structures having patch spacers, and methods of fabricating integrated circuit structures having patch spacers, are described. For example, an integrated circuit structure includes a stack of horizontal nanowires. A gate structure is vertically around the stack of horizontal nanowires, the stack of horizontal nanowires extending laterally beyond the gate structure. An internal gate spacer is between vertically adjacent ones of the stack of horizontal nanowires and laterally adjacent to the gate structure. An external gate spacer is along sides of the gate structure and over the stack of horizontal nanowires, the external gate spacer having one or more patch spacers therein.

Abstract: In some embodiments, a grain analysis system is configured for analyzing a first video frame and outputting respective first film grain information for film grain that is included in the first video frame or configured for analyzing a second video frame and outputting second film grain information. At least one of a grain removal system and a grain synthesis system is included. The grain removal system is configured for removing the film grain from the first video frame using the first film grain information to generate a third video frame corresponding to the first video frame with film grain removed. The grain analysis system is separate from the grain removal system. The grain synthesis system is configured for synthesizing film grain for the third video frame using the first film grain information or the second film grain information. The grain analysis system is separate from the grain synthesis system.

Abstract: Techniques to form semiconductor devices can include one or more via structures having substrate taps. A semiconductor device includes a gate structure around or otherwise on a semiconductor region (or channel region). The gate structure may extend over the semiconductor regions of any number of devices along a given direction. The gate structure may be interrupted, for example, between two transistors with a via structure that extends through an entire thickness of the gate structure and includes a conductive core. The via structure has a conductive foot portion beneath the gate structure and a conductive arm portion extending from the conductive foot portion along a height of the gate structure. The conductive foot portion has a greater width along the given direction than any part of the conductive arm portion. The via structure may further include one or more dielectric layers between the conductive arm portion and the gate structure.

Abstract: Provided are a high-plasticity dual-phase high-entropy alloy (HEA) and a preparation method thereof. The high-plasticity dual-phase HEA has a chemical formula as shown in Formula I: (FeCoNiCr)100-xTix (Formula I), in which, x is in a range of 2.0 to 2.8. A method for preparing the high-plasticity dual-phase HEA is also provided.

Abstract: A system for PET image reconstruction is provided. The system may obtain PET data of a subject. The PET data may be associated with a plurality of coincidence events, which includes scattering events. The system may also generate a preliminary scatter sinogram relating to the scattering events based on the PET data. The system may also generate a target scatter sinogram relating to the scattering events by applying a scatter sinogram generator based on the preliminary scatter sinogram. The target scatter sinogram may have a higher image quality than the preliminary scatter sinogram. The system may further reconstruct a target PET image of the subject based on the PET data and the target scatter sinogram.

Abstract: A phased array transceiver element comprises a local oscillator stage for generating beamformed in-phase and quadrature local oscillator signals, the local oscillator stage comprising a phase shifter connectable to a reference frequency source and applying a first phase shift; a primary frequency multiplier input from the phase shifter and applying a primary frequency multiplication factor; a phase-splitting arrangement input from the primary frequency multiplier and having a first output and a second output, the phase-splitting arrangement applying a second phase shift at the first output and a third phase shift at the second output; a first secondary frequency multiplier input from the first output of the phase-splitting arrangement, having an output for the in-phase local oscillator signal, and applying a secondary frequency multiplication factor; and a second secondary frequency multiplier input from the second output of the phase-splitting arrangement, having an output for the quadrature local oscillator

Abstract: A series of macrocyclic amide compounds and an application thereof. Specifically disclosed are a compound as represented by formula (V) or a pharmaceutically acceptable salt thereof and an application thereof.

Abstract: Techniques are provided to form semiconductor devices where portions of the gate structure (e.g., foot structures) adjacent to the subfins have been removed. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure includes a gate dielectric and a gate electrode. The gate structure may be interrupted, for example, between two transistors with a gate cut that extends through an entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. The gate cut includes dielectric lobe structures that extend outwards from the sidewalls of the gate cut. The lobe structures effectively replace foot structures of the gate structure between the gate cut and subfin portions of the semiconductor fins. Removing the gate foot structures contributes to the reduction of the parasitic capacitance in the semiconductor device.