Patents by Inventor Yangsyu Lin

Yangsyu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250078878
    Abstract: A memory device in an integrated circuit is provided, including an input/output (I/O) circuit, a first memory segment and a second memory segment that separated from the first memory segment in a first direction, a first pair of data lines on a first side of the integrated circuit, extending in the first direction and configured to couple the first memory segment to the I/O circuit, and a second pair of data lines separated from the first pair of data lines in a second direction, different from the first direction, on a second side, opposite to the first side, of the integrated circuit, and configured to couple the second memory segment to the I/O circuit. A first width of the first pair of data lines is different from a second width of the second pair of data lines.
    Type: Application
    Filed: November 19, 2024
    Publication date: March 6, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Sheng WANG, Kao-Cheng LIN, Yangsyu LIN, Yen-Huei CHEN, Cheng Hung LEE, Jonathan Tsung-Yung CHANG
  • Patent number: 12244311
    Abstract: In some aspects of the present disclosure, a circuit in a first power domain is disclosed. In some aspects, the circuit in a first power domain includes a first enable-controlled logic gate coupled to a second circuit in a second power domain different from the first power domain. In some aspects, the circuit in a first power domain includes a feedback loop coupled to the first enable-controlled logic gate, the feedback loop including a first inverter and a second enable-controlled logic gate coupled to the first inverter. In some aspects, the circuit in a first power domain includes a second inverter coupled to the feedback loop.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Je Syu Liu, Chia-Chen Kuo, Yangsyu Lin, Cheng Hung Lee
  • Publication number: 20250063712
    Abstract: A static random access memory (SRAM) periphery circuit includes a first n-type transistor and a second n-type transistor that are disposed in a first well region of first conductivity type, the first well region occupies a first distance in a row direction equal to a bitcell-pitch of an SRAM array. The SRAM periphery circuit includes a first p-type transistor and a second p-type transistor that are disposed in a second well region of second conductivity type. The second well region occupies a second distance in the row direction equal to the bitcell-pitch of the SRAM array. The second well region is disposed adjacent to the first well region in the row direction.
    Type: Application
    Filed: November 6, 2024
    Publication date: February 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yangsyu LIN, Chi-Lung LEE, Chien-Chi TIEN, Chiting CHENG
  • Publication number: 20250007519
    Abstract: In some aspects of the present disclosure, a dual rail circuit is disclosed. In some aspects, the dual rail circuit includes a first circuit in a first power domain. The first circuit comprises an input port and an output port. In some aspects, the dual rail circuit includes a second circuit in a second power domain different from the first power domain. The second circuit coupled to the input port of the first circuit and the output port of the first circuit.
    Type: Application
    Filed: July 31, 2024
    Publication date: January 2, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Je Syu Liu, Chia-Chen Kuo, Yangsyu Lin, Cheng Hung Lee
  • Patent number: 12183417
    Abstract: A memory device in an integrated circuit is provided, including an input/output (I/O) circuit, a first memory segment and a second memory segment that separated from the first memory segment in a first direction, a first pair of data lines on a first side of the integrated circuit, extending in the first direction and configured to couple the first memory segment to the I/O circuit, and a second pair of data lines separated from the first pair of data lines in a second direction, different from the first direction, on a second side, opposite to the first side, of the integrated circuit, and configured to couple the second memory segment to the I/O circuit. A first width of the first pair of data lines is different from a second width of the second pair of data lines.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: December 31, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Sheng Wang, Kao-Cheng Lin, Yangsyu Lin, Yen-Huei Chen, Cheng Hung Lee, Jonathan Tsung-Yung Chang
  • Patent number: 12171092
    Abstract: A static random access memory (SRAM) periphery circuit includes a first n-type transistor and a second n-type transistor that are disposed in a first well region of first conductivity type, the first well region occupies a first distance in a row direction equal to a bitcell-pitch of an SRAM array. The SRAM periphery circuit includes a first p-type transistor and a second p-type transistor that are disposed in a second well region of second conductivity type. The second well region occupies a second distance in the row direction equal to the bitcell-pitch of the SRAM array. The second well region is disposed adjacent to the first well region in the row direction.
    Type: Grant
    Filed: November 9, 2023
    Date of Patent: December 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yangsyu Lin, Chi-Lung Lee, Chien Chi Tien, Chiting Cheng
  • Publication number: 20240397691
    Abstract: The present disclosure describes embodiments of a memory device with a pre-charge circuit. The memory device can include a memory cell, and the pre-charge circuit can include a first transistor and a second transistor. The first transistor includes a first gate terminal, a first source/drain (S/D) terminal coupled to a reference voltage, and a second S/D terminal coupled to a first terminal of the memory cell. The second transistor includes a second gate terminal, a third S/D terminal coupled to the reference voltage, and a fourth S/D terminal coupled to the second terminal of the memory cell. The first and second transistors are configured to pass the reference voltage in response to the control signal being applied to the first and second gate terminals, respectively.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Sheng WANG, Yangsyu Lin, Cheng Hung Lee
  • Publication number: 20240379146
    Abstract: A power control device includes a first switch and a second switch. A first terminal of the first switch is configured to receive a first voltage signal in a first voltage domain, and a first terminal of the second switch is configured to receive a second voltage signal in a second voltage domain different from the a first voltage domain. A second terminal of the second switch is coupled to a second terminal of the first switch, and a control circuit is coupled to control terminals of the first switch and the second switch. The control circuit is configured to turn on the first switch in response to a decrease of a voltage level of the first voltage signal.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Zhi-Hao Chang, Wei-jer Hsieh, Yangsyu Lin
  • Publication number: 20240361819
    Abstract: A circuit includes a power detector and a logic circuit. The power detector is configured to output a first power management signal according to a first power supply signal from a first power supply and a status signal. The circuit is configured to operate in different modes in response to the status signal. The logic circuit is configured to output a second power management signal, according to the first power management signal and the status signal.
    Type: Application
    Filed: July 5, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chen KUO, Yangsyu LIN, Yu-Hao HSU, Cheng Hung LEE, Hung-Jen LIAO
  • Publication number: 20240355384
    Abstract: A memory device includes a memory array having a plurality of memory cells arranged along a plurality of rows extending in a row direction and a plurality of columns extending in a column direction. The memory array also includes a plurality of write assist cells connected to the plurality of memory cells. At least one write assist cell of the plurality of write assist cells is in each of the plurality of columns and connected to respective ones of the plurality of memory cells in a same column.
    Type: Application
    Filed: June 28, 2024
    Publication date: October 24, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yangsyu Lin, Po-Sheng Wang, Cheng Hung Lee, Jonathan Tsung-Yung Chang
  • Publication number: 20240357792
    Abstract: A semiconductor arrangement includes a memory array including bitcells and a peripheral logic block for accessing the bitcells. The peripheral logic block includes a first nanostructure having a first width for providing power to a first logic unit of the peripheral logic block, and a second nanostructure axially aligned with the first nanostructure and having a second width less than the first width for providing power to a second logic unit of the peripheral logic block.
    Type: Application
    Filed: June 28, 2024
    Publication date: October 24, 2024
    Inventors: Po-Sheng WANG, Ru-Yu WANG, Yangsyu LIN, You-Cheng XIAO
  • Patent number: 12119040
    Abstract: A power control device includes a first switch and a second switch. A first terminal of the first switch is configured to receive a first voltage signal in a first voltage domain, and a first terminal of the second switch is configured to receive a second voltage signal in a second voltage domain different from the a first voltage domain. A second terminal of the second switch is coupled to a second terminal of the first switch, and a control circuit is coupled to control terminals of the first switch and the second switch. The control circuit is configured to turn on the first switch in response to a decrease of a voltage level of the first voltage signal.
    Type: Grant
    Filed: June 3, 2022
    Date of Patent: October 15, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Zhi-Hao Chang, Wei-jer Hsieh, Yangsyu Lin
  • Publication number: 20240311543
    Abstract: An integrated circuit includes a first active region of a first set of transistors of a first type, a second active region of a second set of transistors of the first type, a third active region of a third set of transistors of the first type and a fourth active region of a fourth set of transistors of a second type. The first, second, third and fourth active regions extend in a first direction, and are in a first level. The first and second active regions are adjacent to a first boundary and have a first width in a second direction. The third active region is adjacent to a second boundary, and has a second width. The fourth active region is between the second active region and the third active region, and has the first width.
    Type: Application
    Filed: May 28, 2024
    Publication date: September 19, 2024
    Inventors: Po-Sheng WANG, Chao Yuan CHENG, Chien-Chi TIEN, Yangsyu LIN
  • Publication number: 20240312501
    Abstract: A memory circuit includes a control circuit, a memory cell column, first and second bit lines coupled to the memory cell column, a write circuit coupled to a first end of each of the first and second bit lines, and a switching circuit including a first NAND gate including an input terminal coupled to the control circuit, an input terminal coupled to the first bit line, and a first output terminal, a first PMOS transistor coupled between a power supply node and the first bit line and including a gate coupled to the first output terminal, a second NAND gate including an input terminal coupled to the control circuit, an input terminal coupled to the second bit line, and a second output terminal, and a second PMOS transistor coupled between the power supply node and the second bit line and including a gate coupled to the second output terminal.
    Type: Application
    Filed: May 28, 2024
    Publication date: September 19, 2024
    Inventors: Shang-Chi WU, Yangsyu LIN, Chiting CHENG, Jonathan Tsung-Yung CHANG, Mahmut SINANGIL
  • Patent number: 12094529
    Abstract: A memory device includes a memory array having a plurality of memory cells arranged along a plurality of rows extending in a row direction and a plurality of columns extending in a column direction. The memory array also includes a plurality of write assist cells connected to the plurality of memory cells. At least one write assist cell of the plurality of write assist cells is in each of the plurality of columns and connected to respective ones of the plurality of memory cells in a same column.
    Type: Grant
    Filed: July 19, 2023
    Date of Patent: September 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yangsyu Lin, Po-Sheng Wang, Cheng Hung Lee, Jonathan Tsung-Yung Chang
  • Patent number: 12072750
    Abstract: A circuit includes a power detector and a logic circuit. The power detector is configured to output a first power management signal according to a first power supply signal from a first power supply and a status signal. The circuit is configured to operate in different modes in response to the status signal. The logic circuit is configured to output a second power management signal, according to the first power management signal and the status signal.
    Type: Grant
    Filed: June 20, 2023
    Date of Patent: August 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chen Kuo, Yangsyu Lin, Yu-Hao Hsu, Cheng Hung Lee, Hung-Jen Liao
  • Publication number: 20240272666
    Abstract: Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.
    Type: Application
    Filed: April 22, 2024
    Publication date: August 15, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Haruki Mori, Hidehiro Fujiwara, Zhi-Hao Chang, Yangsyu Lin, Yu-Hao Hsu, Yen-Huei Chen, Hung-Jen Liao, Chiting Cheng
  • Patent number: 12048137
    Abstract: A semiconductor arrangement includes a memory array including bitcells and a peripheral logic block for accessing the bitcells. The peripheral logic block includes a first nanostructure having a first width for providing power to a first logic unit of the peripheral logic block, and a second nanostructure axially aligned with the first nanostructure and having a second width less than the first width for providing power to a second logic unit of the peripheral logic block.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: July 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Po-Sheng Wang, Ru-Yu Wang, Yangsyu Lin, You-Cheng Xiao
  • Publication number: 20240201232
    Abstract: A power detection circuit is provided. The power detection circuit includes a comparator circuit operative to generate an output signal in response to an input signal. The output signal is configured to change from a first value to a second value in response to the input signal attaining a first threshold value. The output signal is configured to change from the second value to the first value in response to the input signal subsequently attaining a second threshold value. A current limiting circuit is connected to the comparator circuit and operative to limit a leakage current of the comparator circuit.
    Type: Application
    Filed: February 26, 2024
    Publication date: June 20, 2024
    Inventors: Chia-Chen Kuo, Chiting Cheng, Wei-jer Hsieh, Yangsyu Lin
  • Publication number: 20240203461
    Abstract: Disclosed herein are related to an integrated circuit including a semiconductor layer. In one aspect, the semiconductor layer includes a first region, a second region, and a third region. The first region may include a circuit array, and the second region may include a set of interface circuits to operate the circuit array. A side of the first region may face a first side of the second region along a first direction. The third region may include a set of header circuits to provide power to the set of interface circuits through metal rails extending along a second direction. A side of the third region may face a second side of the second region along the second direction. In one aspect, the first side extending along the second direction is shorter than the second side extending along the first direction, and the metal rails are shorter than the first side.
    Type: Application
    Filed: March 4, 2024
    Publication date: June 20, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Sheng Wang, Yangsyu Lin, Kao-Cheng Lin, Cheng Hung Lee, Jonathan Tsung-Yung Chang