Patents by Inventor Yangsyu Lin

Yangsyu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11562779
    Abstract: A memory circuit includes a reference node configured to carry a reference voltage having a reference voltage level, a power supply node configured to carry a power supply voltage having a power supply voltage level, a bit line coupled with a plurality of memory cells, a write circuit configured to charge the bit line by driving a voltage level on the bit line toward the power supply voltage level with a first current, and a switching circuit coupled between the power supply node and the bit line. The switching circuit is configured to receive the voltage level on the bit line, and responsive to a difference between the voltage level received on the bit line and the power supply voltage level being less than or equal to a threshold value, drive the voltage level on the bit line toward the power supply voltage level with a second current.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: January 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Chi Wu, Yangsyu Lin, Chiting Cheng, Jonathan Tsung-Yung Chang, Mahmut Sinangil
  • Patent number: 11538507
    Abstract: Disclosed herein are related to an integrated circuit including a semiconductor layer. In one aspect, the semiconductor layer includes a first region, a second region, and a third region. The first region may include a circuit array, and the second region may include a set of interface circuits to operate the circuit array. A side of the first region may face a first side of the second region along a first direction. The third region may include a set of header circuits to provide power to the set of interface circuits through metal rails extending along a second direction. A side of the third region may face a second side of the second region along the second direction. In one aspect, the first side extending along the second direction is shorter than the second side extending along the first direction, and the metal rails are shorter than the first side.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: December 27, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Sheng Wang, Yangsyu Lin, Kao-Cheng Lin, Cheng Hung Lee, Jonathan Tsung-Yung Chang
  • Publication number: 20220328097
    Abstract: A write assist circuit is provided. The write assist circuit includes a transistor switch coupled between a bit line voltage node of a cell array and a ground node. An invertor is operative to receive a boost signal responsive to a write enable signal. An output of the invertor is coupled to a gate of the transistor switch. The write assist circuit further includes a capacitor having a first end coupled to the bit line voltage node and a second end coupled to the gate node. The capacitor is operative to drive a bit line voltage of the bit line voltage node to a negative value from the ground voltage in response to the boost signal.
    Type: Application
    Filed: June 27, 2022
    Publication date: October 13, 2022
    Inventors: Wei-jer Hsieh, Chiting Cheng, Yangsyu Lin, Shang-Chi Wu
  • Publication number: 20220302136
    Abstract: A semiconductor arrangement includes a memory array including bitcells and a peripheral logic block for accessing the bitcells. The peripheral logic block includes a first nanostructure having a first width for providing power to a first logic unit of the peripheral logic block, and a second nanostructure axially aligned with the first nanostructure and having a second width less than the first width for providing power to a second logic unit of the peripheral logic block.
    Type: Application
    Filed: August 17, 2021
    Publication date: September 22, 2022
    Inventors: Po-Sheng WANG, Ru-Yu WANG, Yangsyu LIN, You-Cheng XIAO
  • Publication number: 20220285370
    Abstract: A static random access memory (SRAM) periphery circuit includes a first n-type transistor and a second n-type transistor that are disposed in a first well region of first conductivity type, the first well region occupies a first distance in a row direction equal to a bitcell-pitch of an SRAM array. The SRAM periphery circuit includes a first p-type transistor and a second p-type transistor that are disposed in a second well region of second conductivity type. The second well region occupies a second distance in the row direction equal to the bitcell-pitch of the SRAM array. The second well region is disposed adjacent to the first well region in the row direction.
    Type: Application
    Filed: May 23, 2022
    Publication date: September 8, 2022
    Inventors: Yangsyu LIN, Chi-Lung LEE, Chien-Chi TIEN, Chiting CHENG
  • Publication number: 20220276691
    Abstract: A circuit includes a power detector and a logic circuit. The power detector is configured to output a first power management signal according to a first power supply signal from a first power supply and a status signal. The circuit is configured to operate in different modes in response to the status signal. The logic circuit is configured to output a second power management signal, according to the first power management signal and the status signal.
    Type: Application
    Filed: August 24, 2021
    Publication date: September 1, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chen KUO, Yangsyu LIN, Yu-Hao HSU, Cheng Hung LEE, Hung-Jen LIAO
  • Publication number: 20220254385
    Abstract: Memory devices are disclosed that support multiple power ramping sequences or modes. For example, a level shifter device is operably connected to a memory macro in a memory device. The level shifter device receives at least one gating signal. Based on a state of the at least one gating signal, the level shifter device outputs one or more signals that cause or control voltage signals in or received by the memory macro to ramp up, ramp down, or ramp up and ramp down according to one or more power ramping modes.
    Type: Application
    Filed: November 9, 2021
    Publication date: August 11, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Ching Chang, Yangsyu Lin, Yu-Hao Hsu, Cheng Lee
  • Publication number: 20220255538
    Abstract: A clock circuit includes a latch circuit, a memory state latch circuit, a first inverter, a memory state trigger circuit and a second inverter. The latch circuit is configured to latch an enable signal, and to generate a latch output signal based on a first clock signal and a first output clock signal. The memory state latch circuit is configured to latch a second output clock signal responsive to a third output clock signal. The first inverter is configured to generate the first output clock signal responsive to the third output clock signal. The memory state trigger circuit is configured to generate the second output clock signal responsive to the latch output signal. The second inverter is configured to generate the first clock signal responsive to a second clock signal, and configured to control the latch circuit and the memory state trigger circuit based on the first clock signal.
    Type: Application
    Filed: April 29, 2022
    Publication date: August 11, 2022
    Inventors: Hao-I YANG, Cheng Hung LEE, Chen-Lin YANG, Chiting CHENG, Fu-An WU, Yangsyu LIN
  • Publication number: 20220236894
    Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum voltage signal from among the multiple voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum voltage signal from among the multiple voltage signals to minimize power consumption.
    Type: Application
    Filed: April 11, 2022
    Publication date: July 28, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hao HSU, Cheng Hung LEE, Chen-Lin YANG, Chiting CHENG, Fu-An WU, Hung-Jen LIAO, Jung-Ping YANG, Jonathan Tsung-Yung CHANG, Wei Min CHAN, Yen-Huei CHEN, Yangsyu LIN, Chien-Chen LIN
  • Patent number: 11373702
    Abstract: A write assist circuit is provided. The write assist circuit includes a transistor switch coupled between a bit line voltage node of a cell array and a ground node. An invertor is operative to receive a boost signal responsive to a write enable signal. An output of the invertor is coupled to a gate of the transistor switch. The write assist circuit further includes a capacitor having a first end coupled to the bit line voltage node and a second end coupled to the gate node. The capacitor is operative to drive a bit line voltage of the bit line voltage node to a negative value from the ground voltage in response to the boost signal.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: June 28, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Jer Hsieh, Chiting Cheng, Yangsyu Lin, Shang-Chi Wu
  • Patent number: 11342340
    Abstract: A static random access memory (SRAM) periphery circuit includes a first n-type transistor and a second n-type transistor that are disposed in a first well region of first conductivity type, the first well region occupies a first distance in a row direction equal to a bitcell-pitch of an SRAM array. The SRAM periphery circuit includes a first p-type transistor and a second p-type transistor that are disposed in a second well region of second conductivity type. The second well region occupies a second distance in the row direction equal to the bitcell-pitch of the SRAM array. The second well region is disposed adjacent to the first well region in the row direction.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: May 24, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yangsyu Lin, Chi-Lung Lee, Chien-Chi Tien, Chiting Cheng
  • Patent number: 11323101
    Abstract: A clock circuit includes a latch circuit, a memory state latch circuit, a memory state trigger circuit and a clock trigger circuit. The latch circuit is configured to latch an enable signal, and to generate a latch output signal based on a first clock signal or an output clock signal. The memory state latch circuit is configured to generate the output clock signal responsive to a first control signal. The memory state trigger circuit is coupled to the memory state latch circuit, and configured to adjust the output clock signal responsive to the latch output signal. The clock trigger circuit is coupled to the latch circuit or the memory state trigger circuit by a first node, configured to generate the first clock signal responsive to a second clock signal, and configured to control the latch circuit and the memory state trigger circuit based on the first clock signal.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: May 3, 2022
    Assignee: AIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hao-I Yang, Fu-An Wu, Yangsyu Lin, Chiting Cheng, Cheng Hung Lee, Chen-Lin Yang
  • Patent number: 11301148
    Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: April 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hao Hsu, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu, Hung-Jen Liao, Jung-Ping Yang, Jonathan Tsung-Yung Chang, Wei Min Chan, Yen-Huei Chen, Yangsyu Lin, Chien-Chen Lin
  • Publication number: 20220083089
    Abstract: Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.
    Type: Application
    Filed: November 24, 2021
    Publication date: March 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Haruki Mori, Hidehiro Fujiwara, Zhi-Hao Chang, Yangsyu Lin, Yu-Hao Hsu, Yen-Huei Chen, Hung-Jen Liao, Chiting Cheng
  • Publication number: 20220085035
    Abstract: The present disclosure describes embodiments of a memory device with a pre-charge circuit. The memory device can include a memory cell, and the pre-charge circuit can include a first transistor and a second transistor. The first transistor includes a first gate terminal, a first source/drain (S/D) terminal coupled to a reference voltage, and a second S/D terminal coupled to a first terminal of the memory cell. The second transistor includes a second gate terminal, a third S/D terminal coupled to the reference voltage, and a fourth S/D terminal coupled to the second terminal of the memory cell. The first and second transistors are configured to pass the reference voltage in response to the control signal being applied to the first and second gate terminals, respectively.
    Type: Application
    Filed: December 17, 2020
    Publication date: March 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Sheng WANG, Yangsyu LIN, Cheng Hung LEE
  • Patent number: 11264066
    Abstract: The present disclosure describes various exemplary memory storage devices that can be programmed to write electronic data into one or more memory cells in a write mode of operation and/or to read the electronic data from the one or more memory cells in a read mode of operation. The various exemplary memory storage devices can select various control lines to read the electronic data from the one or more memory cells onto data lines and/or to write the electronic data from these data lines into the one or more memory cells. In some situations, these data lines are charged, also referred to as pre-charged, to a first logical value, such as a logical one, before the various exemplary memory storage devices write the electronic data into the one or more memory cells. During this pre-charging of these data lines, the various exemplary memory storage devices electrically isolate these data lines from specialized circuitry within these exemplary memory storage devices.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Chi Wu, Cheng Hung Lee, Chien-Kuo Su, Chiting Cheng, Yu-Hao Hsu, Yangsyu Lin
  • Publication number: 20220026475
    Abstract: A power detection circuit is provided. The power detection circuit includes a comparator circuit operative to generate an output signal in response to an input signal. The output signal is configured to change from a first value to a second value in response to the input signal attaining a first threshold value. The output signal is configured to change from the second value to the first value in response to the input signal subsequently attaining a second threshold value. A current limiting circuit is connected to the comparator circuit and operative to limit a leakage current of the comparator circuit.
    Type: Application
    Filed: July 22, 2020
    Publication date: January 27, 2022
    Inventors: Chia-Chen Kuo, Chiting Cheng, Wei-jer Hsieh, Yangsyu Lin
  • Patent number: 11199866
    Abstract: Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: December 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Haruki Mori, Hidehiro Fujiwara, Zhi-Hao Chang, Yangsyu Lin, Yu-Hao Hsu, Yen-Huei Chen, Hung-Jen Liao, Chiting Cheng
  • Patent number: 11200926
    Abstract: A dual rail memory operable at a first voltage and a second voltage is disclosed. The dual rail memory includes: a memory array operates at the first voltage; a word line driver circuit configured to drive a word line of the memory array to the first voltage; a data path configured to transmit an input data signal or an output data signal, wherein the data path includes a first level shifter for transferring the input data signal from the second voltage to the first voltage; and a control circuit configured to provide control signals to the memory array, the word line driver circuit and the data path, wherein the control circuit includes a second level shifter for transferring an input control signal from the second voltage to the first voltage; wherein the data path and the control circuit are configured to operate at both the first and second voltages.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: December 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chiting Cheng, Yangsyu Lin
  • Patent number: 11189341
    Abstract: A memory device includes a plurality of memory cells arranged in an array having a plurality of rows and a plurality of columns. A first word line is connected to a first plurality of the memory cells of a first row of the array, and a second word line is connected to a second plurality of the memory cells of the first row of the array. In some examples, the plurality of memory cells are arranged in or on a substrate, and the first word line is formed in a first layer of the substrate and the second word line is formed in a second layer of the substrate.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: November 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yangsyu Lin, Chiting Cheng