Patents by Inventor Yangsyu Lin
Yangsyu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200388308Abstract: The present disclosure describes various exemplary memory storage devices that can be programmed to write electronic data into one or more memory cells in a write mode of operation and/or to read the electronic data from the one or more memory cells in a read mode of operation. The various exemplary memory storage devices can select various control lines to read the electronic data from the one or more memory cells onto data lines and/or to write the electronic data from these data lines into the one or more memory cells. In some situations, these data lines are charged, also referred to as pre-charged, to a first logical value, such as a logical one, before the various exemplary memory storage devices write the electronic data into the one or more memory cells. During this pre-charging of these data lines, the various exemplary memory storage devices electrically isolate these data lines from specialized circuitry within these exemplary memory storage devices.Type: ApplicationFiled: August 21, 2020Publication date: December 10, 2020Inventors: Shang-Chi WU, Cheng Hung LEE, Chien-Kuo SU, Chiting CHENG, Yu-Hao HSU, Yangsyu LIN
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Patent number: 10847210Abstract: A memory device includes a plurality of memory cells arranged in an array having a plurality of rows and a plurality of columns. A first word line is connected to a first plurality of the memory cells of a first row of the array, and a second word line is connected to a second plurality of the memory cells of the first row of the array. In some examples, the plurality of memory cells are arranged in or on a substrate, and the first word line is formed in a first layer of the substrate and the second word line is formed in a second layer of the substrate.Type: GrantFiled: February 26, 2019Date of Patent: November 24, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yangsyu Lin, Chiting Cheng
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Patent number: 10818677Abstract: A static random access memory (SRAM) periphery circuit includes a first n-type transistor and a second n-type transistor that are disposed in a first well region of first conductivity type, the first well region occupies a first distance in a row direction equal to a bitcell-pitch of an SRAM array. The SRAM periphery circuit includes a first p-type transistor and a second p-type transistor that are disposed in a second well region of second conductivity type. The second well region occupies a second distance in the row direction equal to the bitcell-pitch of the SRAM array. The second well region is disposed adjacent to the first well region in the row direction.Type: GrantFiled: July 3, 2019Date of Patent: October 27, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yangsyu Lin, Chi-Lung Lee, Chien-Chi Tien, Chiting Cheng
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Patent number: 10811085Abstract: A dual rail device includes a first power domain circuit coupled to a first power supply through a first header control switch and a second power domain circuit coupled to a second power supply. The first and second power supplies have different steady-state voltage levels. The first power domain circuit is interfaced to the second power domain circuit. The device also includes a power detector circuit for providing a control signal for the first header control switch responsive to a voltage level of the second power supply.Type: GrantFiled: September 24, 2019Date of Patent: October 20, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yangsyu Lin, Chiting Cheng
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Patent number: 10762934Abstract: The present disclosure describes various exemplary memory storage devices that can be programmed to write electronic data into one or more memory cells in a write mode of operation and/or to read the electronic data from the one or more memory cells in a read mode of operation. The various exemplary memory storage devices can select various control lines to read the electronic data from the one or more memory cells onto data lines and/or to write the electronic data from these data lines into the one or more memory cells. In some situations, these data lines are charged, also referred to as pre-charged, to a first logical value, such as a logical one, before the various exemplary memory storage devices write the electronic data into the one or more memory cells. During this pre-charging of these data lines, the various exemplary memory storage devices electrically isolate these data lines from specialized circuitry within these exemplary memory storage devices.Type: GrantFiled: January 31, 2019Date of Patent: September 1, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shang-Chi Wu, Cheng Hung Lee, Chien-Kuo Su, Chiting Cheng, Yu-Hao Hsu, Yangsyu Lin
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Publication number: 20200234745Abstract: A dual rail memory operable at a first voltage and a second voltage is disclosed. The dual rail memory includes: a memory array operates at the first voltage; a word line driver circuit configured to drive a word line of the memory array to the first voltage; a data path configured to transmit an input data signal or an output data signal, wherein the data path includes a first level shifter for transferring the input data signal from the second voltage to the first voltage; and a control circuit configured to provide control signals to the memory array, the word line driver circuit and the data path, wherein the control circuit includes a second level shifter for transferring an input control signal from the second voltage to the first voltage; wherein the data path and the control circuit are configured to operate at both the first and second voltages.Type: ApplicationFiled: March 27, 2020Publication date: July 23, 2020Inventors: CHITING CHENG, YANGSYU LIN
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Publication number: 20200195236Abstract: A clock circuit includes a latch circuit, a memory state latch circuit, a memory state trigger circuit and a clock trigger circuit. The latch circuit is configured to latch an enable signal, and to generate a latch output signal based on a first clock signal. The memory state latch circuit is coupled to the latch circuit, and generates an output clock signal responsive to a first control signal. The memory state trigger circuit is coupled to the memory state latch circuit, and adjusts the output clock signal responsive to the latch output signal or a reset signal. The clock trigger circuit is coupled to the latch circuit and the memory state trigger circuit by a first node, configured to generate the first clock signal responsive to a second clock signal, and configured to control the latch circuit and the memory state trigger circuit based on the first clock signal.Type: ApplicationFiled: February 25, 2020Publication date: June 18, 2020Inventors: Hao-I YANG, Cheng Hung LEE, Chen-Lin YANG, Chiting CHENG, Fu-An WU, Yangsyu LIN
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Publication number: 20200176053Abstract: A memory system includes a first array (of memory cells) and a second array (of write assist circuits) arranged into columns each including a bit line and a bit_bar line coupled to corresponding memory cells of the first array and a corresponding at least one write assist circuit of the second array, each write assist circuit including: latch and memory-adapted third and fourth NMOS transistors. The latch includes: memory-adapted first PMOS and first NMOS transistors connected in series between a power-supply voltage and a first node selectively connectable to a ground voltage; and memory-adapted second PMOS transistor and second NMOS transistors connected in series between the power-supply voltage and a second node selectively connectable to ground voltage. The third NMOS transistor is connected in series between the first node and ground voltage; and the fourth NMOS transistor connected in series between the second node and ground voltage.Type: ApplicationFiled: February 3, 2020Publication date: June 4, 2020Inventors: Yangsyu LIN, Chiting CHENG, Jonathan Tsung-Yung CHANG, Shang-Chi WU
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Publication number: 20200135269Abstract: A write assist circuit is provided. The write assist circuit includes a transistor switch coupled between a bit line voltage node of a cell array and a ground node. An invertor is operative to receive a boost signal responsive to a write enable signal. An output of the invertor is coupled to a gate of the transistor switch. The write assist circuit further includes a capacitor having a first end coupled to the bit line voltage node and a second end coupled to the gate node. The capacitor is operative to drive a bit line voltage of the bit line voltage node to a negative value from the ground voltage in response to the boost signal.Type: ApplicationFiled: October 24, 2019Publication date: April 30, 2020Inventors: Wei-jer Hsieh, Chiting Cheng, Yangsyu Lin, Shang-Chi Wu
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Patent number: 10622039Abstract: A dual rail memory operable at a first voltage and a second voltage is disclosed. The dual rail memory includes: a memory array operates at the first voltage; a word line driver circuit configured to drive a word line of the memory array to the first voltage; a data path configured to transmit an input data signal or an output data signal, wherein the data path includes a first level shifter for transferring the input data signal from the second voltage to the first voltage; and a control circuit configured to provide control signals to the memory array, the word line driver circuit and the data path, wherein the control circuit includes a second level shifter for transferring an input control signal from the second voltage to the first voltage; wherein the data path and the control circuit are configured to operate at both the first and second voltages.Type: GrantFiled: December 13, 2018Date of Patent: April 14, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chiting Cheng, Yangsyu Lin
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Publication number: 20200081636Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption.Type: ApplicationFiled: November 15, 2019Publication date: March 12, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Hao HSU, Cheng Hung LEE, Chen-Lin YANG, Chiting CHENG, Fu-An WU, Hung-Jen LIAO, Jung-Ping YANG, Jonathan Tsung-Yung CHANG, Wei Min CHAN, Yen-Huei CHEN, Yangsyu LIN, Chien-Chen LIN
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Patent number: 10574213Abstract: A clock circuit includes a first latch circuit, second latch circuit, first trigger circuit and second trigger circuit. The first latch circuit is configured to generate a first latch output signal based on at least a trigger signal or an output clock signal. The second latch circuit is coupled to the first latch circuit, and configured to generate the output clock signal responsive to a control signal. The first trigger circuit is coupled to the second latch circuit, and configured to adjust the output clock signal responsive to at least the first latch output signal. The second trigger circuit is coupled to the first latch circuit and the first trigger circuit by a first node, configured to generate the trigger signal responsive to an input clock signal, and configured to control the first latch circuit and the first trigger circuit based on at least the trigger signal.Type: GrantFiled: November 30, 2018Date of Patent: February 25, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hao-I Yang, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu, Yangsyu Lin
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Patent number: 10553275Abstract: A write assist circuit includes: a memory-adapted latch and memory-adapted third and fourth NMOS transistors. The latch includes: a memory-adapted first PMOS transistor and a memory-adapted first NMOS transistor connected in series between a power-supply voltage and a first node, the first node being selectively connectable to a ground voltage; and a memory-adapted second PMOS transistor and a memory-adapted second NMOS transistor connected in series between the power-supply voltage and the second node, the second node being selectively connectable to the ground voltage. The third NMOS transistor is connected in series between the first node and the ground voltage; and the fourth NMOS transistor connected in series between the second node and the ground voltage. A gate electrode of each of the third and fourth transistors is connected to a latch-enable signal-line thereby for controlling the memory-adapted latch.Type: GrantFiled: April 10, 2018Date of Patent: February 4, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yangsyu Lin, Chiting Cheng, Jonathan Tsung-Yung Chang, Shang-Chi Wu
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Publication number: 20200020700Abstract: A static random access memory (SRAM) periphery circuit includes a first n-type transistor and a second n-type transistor that are disposed in a first well region of first conductivity type, the first well region occupies a first distance in a row direction equal to a bitcell-pitch of an SRAM array. The SRAM periphery circuit includes a first p-type transistor and a second p-type transistor that are disposed in a second well region of second conductivity type. The second well region occupies a second distance in the row direction equal to the bitcell-pitch of the SRAM array. The second well region is disposed adjacent to the first well region in the row direction.Type: ApplicationFiled: July 3, 2019Publication date: January 16, 2020Inventors: Yangsyu LIN, Chi-Lung LEE, Chien-Chi TIEN, Chiting CHENG
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Publication number: 20200020387Abstract: A dual rail device includes a first power domain circuit coupled to a first power supply through a first header control switch and a second power domain circuit coupled to a second power supply. The first and second power supplies have different steady-state voltage levels. The first power domain circuit is interfaced to the second power domain circuit. The device also includes a power detector circuit for providing a control signal for the first header control switch responsive to a voltage level of the second power supply.Type: ApplicationFiled: September 24, 2019Publication date: January 16, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yangsyu Lin, Chiting Cheng
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Publication number: 20200005835Abstract: The present disclosure describes various exemplary memory storage devices that can be programmed to write electronic data into one or more memory cells in a write mode of operation and/or to read the electronic data from the one or more memory cells in a read mode of operation. The various exemplary memory storage devices can select various control lines to read the electronic data from the one or more memory cells onto data lines and/or to write the electronic data from these data lines into the one or more memory cells. In some situations, these data lines are charged, also referred to as pre-charged, to a first logical value, such as a logical one, before the various exemplary memory storage devices write the electronic data into the one or more memory cells. During this pre-charging of these data lines, the various exemplary memory storage devices electrically isolate these data lines from specialized circuitry within these exemplary memory storage devices.Type: ApplicationFiled: January 31, 2019Publication date: January 2, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shang-Chi WU, Cheng Hung LEE, Chien-Kuo SU, Chiting CHENG, Yu-Hao HSU, Yangsyu LIN
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Patent number: 10503421Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to control minimize power consumption.Type: GrantFiled: March 28, 2018Date of Patent: December 10, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Hao Hsu, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu, Hung-Jen Liao, Jung-Ping Yang, Jonathan Tsung-Yung Chang, Wei Min Chan, Yen-Huei Chen, Yangsyu Lin, Chien-Chen Lin
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Patent number: 10490263Abstract: A dual rail device includes a first power domain circuit coupled to a first power supply through a first header control switch and a second power domain circuit coupled to a second power supply. The first and second power supplies have different steady-state voltage levels. The first power domain circuit is interfaced to the second power domain circuit. The device also includes a power detector circuit for providing a control signal for the first header control switch responsive to a voltage level of the second power supply.Type: GrantFiled: November 6, 2018Date of Patent: November 26, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yangsyu Lin, Chiting Cheng
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Publication number: 20190311765Abstract: A memory device includes a plurality of memory cells arranged in an array having a plurality of rows and a plurality of columns. A first word line is connected to a first plurality of the memory cells of a first row of the array, and a second word line is connected to a second plurality of the memory cells of the first row of the array. In some examples, the plurality of memory cells are arranged in or on a substrate, and the first word line is formed in a first layer of the substrate and the second word line is formed in a second layer of the substrate.Type: ApplicationFiled: February 26, 2019Publication date: October 10, 2019Inventors: Yangsyu Lin, Chiting Cheng
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Publication number: 20190304520Abstract: A circuit includes a voltage node, a plurality of memory cells, a bit line coupled with the plurality of memory cells, and a switching circuit coupled between the voltage node and the bit line. The switching circuit is configured to couple the voltage node with the bit line responsive to a voltage level on the bit line.Type: ApplicationFiled: March 28, 2018Publication date: October 3, 2019Inventors: Shang-Chi WU, Chiting CHENG, Jonathan Tsung-Yung CHANG, Yangsyu LIN, Mahmut SINANGIL