Abstract: Disclosed in the present application are a logic circuit design method and apparatus, and a storage medium. The method comprises: designing and generating an initial MOSFET-TFET hybrid logic circuit, the MOSFET-TFET hybrid logic circuit comprising several logic gates; in the series branch of the initial MOSFET-TFET hybrid logic circuit, replacing a first type of TFET with a MOSFET; the first type of TFET being directly grounded or connected to a power supply and not directly connected to the output ends of the logic gates. The logic circuit design method of the present application overcomes the defect of excessive current attenuation caused by the TFET in the series branch by replacing the first type of TFET in the series branch of the initial logic circuit with a MOSFET The first type of TFET is a TFET that is directly grounded or connected to a power supply and not directly connected to the output ends of the logic gates.

Abstract: The present application discloses a circuit for extracting a feature, a network and a signal processing system. The circuit includes: one or more instant range of change feature extracting units, which are connected in parallel and configured to extract and classify an instant range of change (IROC) feature from an input of an asynchronous pulse coding in the time domain, the input of the asynchronous pulse coding is a pulse request signal and a pulse direction signal obtained by performing time-domain quantization and coding on an analog signal. By the circuit for extracting a feature according to the present application, the instant range of change of an analog input of the asynchronous pulse coding can be directly extracted and classified in the time domain, converting from the time domain to the frequency domain required by the traditional feature extraction process is avoided, and the power consumption overhead is reduced.

Abstract: The present invention discloses a short-gate tunneling field effect transistor having a non-uniformly doped vertical channel and a fabrication method thereof. The short-gate tunneling field effect transistor has a vertical channel and the channel region is doped in such a slowly-varied and non-uniform manner that a doping concentration in the channel region appears as a Gaussian distribution along a vertical direction and the doping concentration in the channel near the drain region is higher while the doping concentration in the channel near the source region is lower; and double control gates are formed at both sides of the vertical channel and the control gates form an L-shaped short-gate structure, so that a gate underlapped region is formed in the channel near the drain region, and a gate overlapped region is formed at the source region.

Abstract: The present invention discloses a tunneling field effect transistor having a three-side source and a fabrication method thereof, referring to field effect transistor logic devices and circuits in CMOS ultra large scale integrated circuits (ULSI). By means of the strong depletion effect of the three-side source, the transistor can equivalently achieve a steep doping concentration gradient for the source junction, significantly optimizing the sub-threshold slope of the TFET. Meanwhile, the turn-on current of the transistor is boosted. Furthermore, due to a region uncovered by the gate between the gate and the drain, the bipolar conduction effect of the transistor is effectively inhibited, and on the other hand, in the small-size transistor a parasitic tunneling current at the corner of the source junction is inhibited. The fabrication method is simple and can be accurately controlled.

Abstract: Provided are a method for suppressing a leakage current of a tunnel field-effect transistor (TFET), a corresponding device, and a manufacturing method, related to the field of field-effect transistor logic devices and circuits in CMOS ultra large-scale integration (ULSI). By inserting an insulating layer (7) between a source region (10) and a transistor body below a tunneling junction, and by inserting no insulating layer at a tunneling junction between a source region and a channel, a source/drain direct tunneling leakage current in a small-sized TFET device is effectively suppressed, and a threshold slope is effectively improved. The manufacturing method for the corresponding device is completely compatible with an existing CMOS process.

Abstract: The present invention discloses a junction-modulated tunneling field effect transistor and a fabrication method thereof, belonging to a field of field effect transistor logic device and the circuit in connection with CMOS ultra large scale integrated circuit (ULSI). The PN junction provided by a highly-doped source region surrounding three sides of the vertical channel region of the tunneling field effect transistor can deplete effectively the channel region, so that the energy band of the surface channel under the gate is lifted, therefore the device may obtain a steeper energy band and a narrower tunneling barrier width than the conventional TFET when the band-to-band tunneling occurs, equivalently achieving the effect of a steep doping concentration gradient at the source tunneling junction, and thereby the sub-threshold characteristics are significantly improved while the turn-on current of the device is improved relative to the conventional TFET.

Abstract: The present invention discloses a tunneling field effect transistor having a three-side source and a fabrication method thereof, referring to field effect transistor logic devices and circuits in CMOS ultra large scale integrated circuits (ULSI). By means of the strong depletion effect of the three-side source, the transistor can equivalently achieve a steep doping concentration gradient for the source junction, significantly optimizing the sub-threshold slope of the TFET. Meanwhile, the turn-on current of the transistor is boosted. Furthermore, due to a region uncovered by the gate between the gate and the drain, the bipolar conduction effect of the transistor is effectively inhibited, and on the other hand, in the small-size transistor a parasitic tunneling current at the corner of the source junction is inhibited. The fabrication method is simple and can be accurately controlled.

Abstract: The present invention discloses a strip-shaped gate tunneling field effect transistor using composite mechanism and a fabrication method thereof, which belongs to a field of field effect transistor logic devices and circuits in the CMOS ultra large scale integrated circuit (ULSI). According to the tunneling field effect transistor, the energy band of the channel underneath the gate is elevated by means of a change of the gate morphology and the PN junction depletion effect occurred at both sides of the strip-shaped gate, so that the sub-threshold characteristics of the transistor are improved. Meanwhile, the on-state current of the transistor is effectively increased by means of the composite mechanism introduced by the two parts of the doped source region.

Abstract: The present invention discloses a short-gate tunneling field effect transistor having a non-uniformly doped vertical channel and a fabrication method thereof. The short-gate tunneling field effect transistor has a vertical channel and the channel region is doped in such a slowly-varied and non-uniform manner that a doping concentration in the channel region appears a Gaussian distribution along a vertical direction and the doping concentration in the channel near the drain region is higher while the doping concentration in the channel near the source region is lower; and double control gates are formed at both sides of the vertical channel and the control gates form an L-shaped short-gate structure, so that a gate underlapped region is formed in the channel near the drain region, and a gate overlapped region is formed at the source region.

Abstract: A resistive memory having a leakage inhibiting characteristic and a method for fabricating the same, which can suppress a sneak current in a large scaled crossing array of a RRAM. A memory cell forming the resistive memory comprises a lower electrode, a first semiconductor-type oxide layer, a resistive material layer, a second semiconductor-type oxide layer and an upper electrode which are sequentially stacked. Each of the semiconductor-type oxide layers may be a semiconductor-type metal oxide or a semiconductor-type non-metal oxide. The sneak current may be effectively reduced by means of a Schottky barrier formed between the semiconductor-type oxide layer and the metal electrode, the fabrication process is easy to be implemented, and a high device integration degree can be achieved.

Abstract: The present invention provides a tunneling field effect transistor and a method for fabricating the same which refer to a field effect transistor logic device and circuit in a CMOS ultra-large integrated circuit (ULSI). The inventive concept of the invention lies in that, in a case of an N-type transistor, a side portion of a doped source region adjacent to an edge of the control gate is further implanted with P+ impurities on a basis of the doped source region being initially doped N? impurities, so that the initial N? impurities in the implanted portion are completely compensated by the P+ impurities, and in a case of a P-type transistor, a side portion of the doped source region adjacent to an edge of the control gate is implanted with N+ impurities on a basis of the doped source region being initially doped P? impurities, so that the initial P? impurities in the implanted portion are completely compensated by the N+ impurities.

Abstract: The present invention provides a tunneling field effect transistor and a method for fabricating the same which refer to a field effect transistor logic device and circuit in a CMOS ultra-large integrated circuit (ULSI). The inventive concept of the invention lies in that, in a case of an N-type transistor, a side portion of a doped source region adjacent to an edge of the control gate is further implanted with P+ impurities on a basis of the doped source region being initially doped N? impurities, so that the initial N? impurities in the implanted portion are completely compensated by the P+ impurities, and in a case of a P-type transistor, a side portion of the doped source region adjacent to an edge of the control gate is implanted with N+ impurities on a basis of the doped source region being initially doped P? impurities, so that the initial P? impurities in the implanted portion are completely compensated by the N+ impurities.

Abstract: The present invention discloses a hexagonal programmable array based on a silicon nanowire field effect transistor and a method for fabricating the same. The array includes a nanowire device, a nanowire device connection region and a gate connection region, wherein, the nanowire device has a cylinder shape, and includes a silicon nanowire channel, a gate dielectric layer, and a gate region, the nanowire channel being surrounded by the gate dielectric layer, and the gate dielectric layer being surrounded by the gate region; the nanowire devices are arranged in a hexagon shape to form programming unit, the nanowire device connection region is a connection node of three nanowire devices and secured to a silicon supporter. The present invention can achieve a complex control logic of interconnections and is suitable for a digital/analog and a mixed-signal circuit having a high integration degree and a high speed.

Abstract: The present invention discloses a strip-shaped gate-modulated tunneling field effect transistor with double-diffusion and a preparation method thereof, belonging to a field of CMOS field effect transistor logic device and the circuit.

Abstract: Proposed is a method for testing the density and location of a gate dielectric layer trap of a semiconductor device. The testing method tests the trap density and two-dimensional trap location in the gate dielectric layer of a semiconductor device with a small area (the effective channel area is less than 0.5 square microns) using the gate leakage current generated by a leakage path. The present invention is especially suitable for testing a device with an ultra-small area (the effective channel area is less than 0.05 square microns). The present method can obtain trap distribution scenarios of the gate dielectric layer in the case of different materials and different processes.

Abstract: The present invention discloses a strip-shaped gate-modulated tunneling field effect transistor and a preparation method thereof, belonging to a field of field effect transistor logic device and the circuit in CMOS ultra large scale integrated circuit (ULSI). The tunneling field effect transistor includes a control gate, a gate dielectric layer, a semiconductor substrate, a highly-doped source region and a highly-doped drain region, where the highly-doped source region and the highly-doped drain region lie on both sides of the control gate, respectively, the control gate has a strip-shaped structure with a gate length greater than a gate width, and at one side thereof is connected to the highly-doped drain region and at the other side thereof extends laterally into the highly-doped source region; a region located below the control gate is a channel region; and the gate width of the control gate is less than twice width of a source depletion layer.

Abstract: The present invention discloses a strip-shaped gate-modulated tunneling field effect transistor with double-diffusion and a preparation method thereof, belonging to a field of CMOS field effect transistor logic device and the circuit.

Abstract: Disclosed herein is a method for fabricating a complementary tunneling field effect transistor based on a standard CMOS IC process, which belongs to the field of logic devices and circuits of field effect transistors in ultra large scaled integrated (ULSI) circuits. In the method, an intrinsic channel and body region of a TFET are formed by means of complementary P-well and N-well masks in the standard CMOS IC process to form a well doping, a channel doping and a threshold adjustment by implantation. Further, a bipolar effect in the TFET can be inhibited via a distance between a gate and a drain on a layout so that a complementary TFET is formed. In the method according to the invention, the complementary tunneling field effect transistor (TFET) can be fabricated by virtue of existing processes in the standard CMOS IC process without any additional masks and process steps.

Abstract: The present invention discloses a tunneling current amplification transistor, which relates to an area of field effect transistor logic devices in CMOS ultra large scale semiconductor integrated circuits (ULSI). The tunneling current amplification transistor includes a semiconductor substrate, a gate dielectric layer, an emitter, a drain, a floating tunneling base and a control gate, wherein the drain, the floating tunneling base and the control gate forms a conventional TFET structure, and a doping type of the emitter is opposite to that of the floating tunneling base. A position of the emitter is at the other side of the floating tunneling base with respect to the drain. A type of the semiconductor between the emitter and the floating tunneling base is the same as that of the floating tunneling base.

Abstract: A method for testing trap density in a gate dielectric layer of a semiconductor device having no substrate contact is provided in the invention. A source and a drain of the device are bilateral symmetric, and probes and cables of a test instrument connecting to the source and the drain are bilateral symmetric. Firstly, bias settings at the gate, the source and the drain are controlled so that the device is under an initial state that an inversion layer is not formed and traps in the gate dielectric layer impose no confining effects on charges.