Abstract: A Pseudomonas monteilii strain with salinity-alkalinity tolerance is provided. The strain is Pseudomonas monteilii 9-2, which has been deposited in China General Microbiological Culture Collection Center (CGMCC) on Oct. 25, 2021, with an accession number of CGMCC No. 23666; and an internal transcribed spacer (ITS) sequence is shown in SEQ ID NO: 1. This application further provides an application of the Pseudomonas monteilii strain in the degradation of petroleum hydrocarbons in a saline-alkali environment.

Abstract: A semiconductor device, a memory system, and a fabricating method are provided. The semiconductor device comprises a memory structure bonded with a circuit structure. The memory structure comprises: first transistors each comprising a semiconductor body extending in a vertical direction, a semiconductor layer on a lateral side of the first transistors, a first isolation structure extending through the semiconductor layer and laterally encircling a first portion of the semiconductor layer, a first contact structure extending through the first portion of the semiconductor layer, and a first contact pad above the first portion of the semiconductor layer and connected with the first contact structure. A lateral dimension of the first contact pad is less than a lateral dimension of the first portion of the semiconductor layer. The circuit structure comprises a second transistor, and the first contact pad is electrically connected to the second transistor by the first contact structure.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells, a first peripheral circuit of the array of memory cells, and a polysilicon layer between the array of memory cells and the first peripheral circuit. The first peripheral circuit includes a first transistor. The second semiconductor structure includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, and a first bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells. The second semiconductor structure includes a first peripheral circuit of the array of memory cells. The first peripheral circuit includes a first transistor. A third semiconductor structure includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor. The first semiconductor structure, the second semiconductor structure, and the third semiconductor structure are stacked over one another.

Abstract: A laser radar integrated device, including a cover plate (Q10, M10, N20, P60), a fixed support (Q20), a lifting structure (Q30), a pop-up structure (Q50), a laser radar (Q60), and a controller (Q70, D50). The cover plate (Q10, M10, N20, P60) is located on a vehicle fender (Q80, M200, N200, P200) and matches with the size of an opening in the fender (Q80, M200, N200, P200); the fixed support (Q20), the lifting structure (Q30), the pop-up structure (Q50), the laser radar (Q60) and the controller (Q70, D50) are located inside the fender (Q80, M200, N200, P200); the lifting structure (Q30) is disposed on the fixed support (Q20) and connected to the cover plate (Q10, M10, N20, P60); the laser radar (Q60) is disposed on the pop-up structure (Q50) which is disposed on the fixed support (Q20). Also disclosed is a vehicle provided with a laser radar integrated device.

Abstract: A memory device includes a memory array structure, a first peripheral circuit, and a second peripheral circuit. The memory array structure includes a vertical transistor having a first terminal and a second terminal, a storage unit having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor. The first peripheral circuit is disposed at one side of the memory array structure and includes a first side in contact with the memory array structure and a second side opposite to the first side in a first direction. The second peripheral circuit is disposed in contact with the second side of the first peripheral circuit away from the memory array structure.

Abstract: A memory device includes a memory array structure including a vertical transistor having a first terminal and a second terminal, a storage unit having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor, a first peripheral circuit coupled to a first surface of the memory array structure, and a second peripheral circuit coupled to a second surface of the memory array structure opposite to the first surface. The vertical transistor includes a semiconductor body extending in a first direction, and a gate structure coupled to at least one side of the semiconductor body.

Abstract: A memory device includes a memory array and a peripheral circuit coupled to the memory array. The memory array includes a vertical transistor having a first terminal and a second terminal, a storage unit having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor. The vertical transistor includes a semiconductor body extending in a first direction, and a gate structure coupled to at least one side of the semiconductor body. The vertical transistor is disposed between the bit line and the storage unit along the first direction.

Abstract: A catalyst for producing dibasic amine by hydrogenation of dibasic nitrile contains the following components or reaction product thereof: a) an active component, wherein the active component comprises Ni and/or an oxide thereof; b) an auxiliary, wherein the auxiliary comprises one or more of Mg, Cu, Co, Zn, Zr, Mo and/or oxides thereof; C) support, wherein the relative content of ?-NiO in the catalyst is less than 2.0 a.u. A process for producing dibasic amine by hydrogenation of dibasic nitrile is also provided.

Abstract: A semiconductor device and methods for forming the same are provided. The semiconductor device includes an array of vertical transistors. Each transistor includes a semiconductor body extending in a vertical direction, and a gate structure located adjacent to a sidewall of the semiconductor body. The gate structures of each row of vertical transistors are connected with each other and extend along a first lateral direction to form a word line. A first word line of a first row of vertical transistors is located at a first side of the semiconductor bodies of the first row of vertical transistors along a second lateral direction perpendicular to the first lateral direction; and a second word line of a second row of vertical transistors adjacent to the first row of vertical transistors is located at a second side of the semiconductor bodies of the second row of vertical transistors along the second lateral direction.

Abstract: A three-dimensional (3D) memory device and a fabricating method thereof are disclosed. The 3D memory device can comprise an array of memory cells. Each memory cell can comprise a capacitor and a vertical transistor. The vertical transistor can comprise a semiconductor body extending in a vertical direction and in contact with the capacitor, and a three-sided gate structure surrounding the semiconductor body from three lateral directions. The 3D memory device can further comprise a memory controller configured to control the array of memory cells.

Abstract: A semiconductor device and methods for forming the same are provided. The method includes: forming a plurality of first trenches having a first width during forming a plurality of grooves having a second width less than the first width, each of the plurality of first trenches and the plurality of grooves extending laterally along a first lateral direction and vertically in an upper portion of a semiconductor layer, the plurality of first trenches and the plurality of grooves being alternatively arranged along a second lateral direction different from the first lateral direction; forming a spacer in each groove, where the spacer is laterally extending along the first lateral direction; and forming two disconnected conductive structures in each first trench, the disconnected conductive structures laterally extending in parallel along the first lateral direction.

Abstract: System, method, and various embodiments for providing a data access and recommendation system are described herein. An embodiment operates by identifying a column access of one or more data values of a first column of a plurality of columns of a table of a database during a sampling period. A count of how many of the one or more data values are accessed during the column access are recorded. A first counter is incremented by the count. The sampling period is determined to have expired. A load recommendation on how to load data values into the first column based on the first counter is computed. The load recommendation for implementation into the database for one or more subsequent column accesses is provided.

Abstract: Provided is a cardiovascular implant based on in-situ regulation of immune response and a method for making the same, belonging to the technical field of biomedicine. The cardiovascular implant includes a cardiovascular implant body and H4000-CD25/dcas9 sustained-release nanoparticles modified on the cardiovascular implant body; the H4000-CD25/dcas9 sustained-release nanoparticles include an H4000 plasmid nanocarrier (Engreen), an anti-CD25 antibody, and a dcas9 plasmid sequence; a method for preparing the cardiovascular implant includes: constructing a cardiovascular implant body, preparing an H4000-CD25 nanotransfection vector, preparing H4000-CD25/dcas9 sustained-release nanoparticles, and conjugating the H4000-CD25/dcas9 sustained-release nanoparticles on the cardiovascular implant body.

Abstract: The present invention provides a prediction method and system of high slope deformation. First, historical deformation data of each period of each part of a high slope is obtained as sample data; the sample data is divided into training samples and test samples; then a parameter group of a Support Vector Machine (SVM) model is optimized by using the training samples and a particle Swarm Optimization (PSO) algorithm to determine an optimal parameter group of the SVM model, to obtain a trained SVM model; whether the trained SVM model satisfies a condition is verified by using the test samples, and when the SVM model does not satisfy the condition, an optimal parameter group of the SVM model is re-determined; and finally the deformation of each area of the high slope is predicted by using the SVM model that satisfies the condition.

Abstract: A three-dimensional (3D) memory device includes a plurality of memory stacks arranged along a first direction, and a dummy block structure disposed between two adjacent memory stacks. Each memory stack includes a plurality of first conductive layers and a plurality of first dielectric layers alternately stacked along a second direction perpendicular to the first direction. A channel structure extends through the plurality of first conductive layers and the plurality of first dielectric layers along the second direction. A first isolation structure is disposed between the dummy block structure and one of the plurality of memory stacks. A substrate is disposed under the plurality of memory stacks, the dummy block structure, and the first isolation structure. A second isolation structure is disposed in the substrate extending along the second direction.

Abstract: The present application discloses a graph neural network processing method and associated machine and system. The graph neural network method is used for a master, wherein the master, a first worker and a second worker train the graph neural network in a distributed environment. The method includes: receiving a first request from the first worker and a second request from the second worker, wherein the first worker sends the first request to the master to obtain at least an attribute of a first requested node, and the second worker sends a second request to the master to obtain at least an attribute of a second requested node; determining whether the first requested node and the second requested node are the same nodes and generating a determination result accordingly; and selectively performing broadcast or unicast to the first worker and the second worker, at least based on the determination result.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes an array of memory cells, a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction, and a plurality of word lines coupled to the memory cells and each extending in a third direction perpendicular to the first direction and the second direction. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes an array of memory cells and a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. The vertical transistor includes a semiconductor body extending in the first direction, and a gate structure in contact with two opposite sides of the semiconductor body in the second direction. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction.