Patents by Inventor Yann Lee

Yann Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10622301
    Abstract: A method for manufacturing a semiconductor device includes forming a first interconnect level having a conductive metal layer formed in a first dielectric layer. In the method, a cap layer is formed on the first interconnect level, and a second interconnect level including a second dielectric layer is formed on the cap layer. The method also includes forming a third interconnect level including a third dielectric layer on the second interconnect level. An opening is formed through the second and third interconnect levels and over the conductive metal layer. Sides of the opening are lined with a spacer material, and a portion of the cap layer at a bottom of the opening is removed from a top surface of the conductive metal layer. The spacer material is removed from the opening, and a conductive material layer is deposited in the opening on the conductive metal layer.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: April 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yongan Xu, Junli Wang, Yann Mignot, Joe Lee
  • Publication number: 20200066632
    Abstract: A method for manufacturing a semiconductor device includes forming a first interconnect level having a conductive metal layer formed in a first dielectric layer. In the method, a cap layer is formed on the first interconnect level, and a second interconnect level including a second dielectric layer is formed on the cap layer. The method also includes forming a third interconnect level including a third dielectric layer on the second interconnect level. An opening is formed through the second and third interconnect levels and over the conductive metal layer. Sides of the opening are lined with a spacer material, and a portion of the cap layer at a bottom of the opening is removed from a top surface of the conductive metal layer. The spacer material is removed from the opening, and a conductive material layer is deposited in the opening on the conductive metal layer.
    Type: Application
    Filed: November 1, 2019
    Publication date: February 27, 2020
    Inventors: Yongan Xu, Junli Wang, Yann Mignot, Joe Lee
  • Publication number: 20200058585
    Abstract: A method for manufacturing a semiconductor device includes forming a first interconnect level having a conductive metal layer formed in a first dielectric layer. In the method, a cap layer is formed on the first interconnect level, and a second interconnect level including a second dielectric layer is formed on the cap layer. The method also includes forming a third interconnect level including a third dielectric layer on the second interconnect level. An opening is formed through the second and third interconnect levels and over the conductive metal layer. Sides of the opening are lined with a spacer material, and a portion of the cap layer at a bottom of the opening is removed from a top surface of the conductive metal layer. The spacer material is removed from the opening, and a conductive material layer is deposited in the opening on the conductive metal layer.
    Type: Application
    Filed: August 17, 2018
    Publication date: February 20, 2020
    Inventors: Yongan Xu, Junli Wang, Yann Mignot, Joe Lee
  • Patent number: 10535567
    Abstract: A method for manufacturing a semiconductor device includes forming a hardmask layer on a substrate, patterning the hardmask layer to form a plurality of patterned hardmask portions on the substrate, depositing a dummy hardmask layer on the substrate, patterning the dummy hardmask layer to form a plurality of patterned dummy hardmask portions on the substrate, wherein each of the plurality of patterned dummy hardmask portions is positioned adjacent respective outermost patterned hardmask portions of the plurality of patterned hardmask portions, and transferring a pattern of the plurality of patterned hardmask portions and the plurality of patterned dummy hardmask portions to the substrate to form a plurality of fins and a plurality of dummy fins from the substrate.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: January 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Peng Xu, Kangguo Cheng, Yann Mignot, Choonghyun Lee
  • Publication number: 20190252262
    Abstract: A method for manufacturing a semiconductor device includes forming a hardmask layer on a substrate, patterning the hardmask layer to form a plurality of patterned hardmask portions on the substrate, depositing a dummy hardmask layer on the substrate, patterning the dummy hardmask layer to form a plurality of patterned dummy hardmask portions on the substrate, wherein each of the plurality of patterned dummy hardmask portions is positioned adjacent respective outermost patterned hardmask portions of the plurality of patterned hardmask portions, and transferring a pattern of the plurality of patterned hardmask portions and the plurality of patterned dummy hardmask portions to the substrate to form a plurality of fins and a plurality of dummy fins from the substrate.
    Type: Application
    Filed: April 23, 2019
    Publication date: August 15, 2019
    Inventors: Peng Xu, Kangguo Cheng, Yann Mignot, Choonghyun Lee
  • Publication number: 20190252263
    Abstract: A method for manufacturing a semiconductor device includes forming a hardmask layer on a substrate, patterning the hardmask layer to form a plurality of patterned hardmask portions on the substrate, depositing a dummy hardmask layer on the substrate, patterning the dummy hardmask layer to form a plurality of patterned dummy hardmask portions on the substrate, wherein each of the plurality of patterned dummy hardmask portions is positioned adjacent respective outermost patterned hardmask portions of the plurality of patterned hardmask portions, and transferring a pattern of the plurality of patterned hardmask portions and the plurality of patterned dummy hardmask portions to the substrate to form a plurality of fins and a plurality of dummy fins from the substrate.
    Type: Application
    Filed: April 23, 2019
    Publication date: August 15, 2019
    Inventors: Peng Xu, Kangguo Cheng, Yann Mignot, Choonghyun Lee
  • Patent number: 10361125
    Abstract: A method for manufacturing a semiconductor device includes forming a hardmask layer on a substrate, patterning the hardmask layer to form a plurality of patterned hardmask portions on the substrate, depositing a dummy hardmask layer on the substrate, patterning the dummy hardmask layer to form a plurality of patterned dummy hardmask portions on the substrate, wherein each of the plurality of patterned dummy hardmask portions is positioned adjacent respective outermost patterned hardmask portions of the plurality of patterned hardmask portions, and transferring a pattern of the plurality of patterned hardmask portions and the plurality of patterned dummy hardmask portions to the substrate to form a plurality of fins and a plurality of dummy fins from the substrate.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: July 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Peng Xu, Kangguo Cheng, Yann Mignot, Choonghyun Lee
  • Publication number: 20190189519
    Abstract: A method for manufacturing a semiconductor device includes forming a hardmask layer on a substrate, patterning the hardmask layer to form a plurality of patterned hardmask portions on the substrate, depositing a dummy hardmask layer on the substrate, patterning the dummy hardmask layer to form a plurality of patterned dummy hardmask portions on the substrate, wherein each of the plurality of patterned dummy hardmask portions is positioned adjacent respective outermost patterned hardmask portions of the plurality of patterned hardmask portions, and transferring a pattern of the plurality of patterned hardmask portions and the plurality of patterned dummy hardmask portions to the substrate to form a plurality of fins and a plurality of dummy fins from the substrate.
    Type: Application
    Filed: December 19, 2017
    Publication date: June 20, 2019
    Inventors: Peng Xu, Kangguo Cheng, Yann Mignot, Choonghyun Lee
  • Publication number: 20180326142
    Abstract: A portable device for monitoring vascular access status is disclosed. The portable device comprises a measurement device and a monitoring module. The measurement device senses vibration data induced by blood flow over certain part of a vascular access of a subject via a vibration-sensing module, and sends the sensed data to outside via its communication module. The monitor module controls an electronic device to receive the sensed data and determines a vibration evaluation index corresponding to a status of the part of the vascular access. The portable device for monitoring vascular access status of the present disclosed example has advantages of small size, easy to carry, low cost, and so on, so as to be applicable to home vascular access status monitor.
    Type: Application
    Filed: August 1, 2017
    Publication date: November 15, 2018
    Inventors: Chiy-Ferng PERNG, Yi-Chung CHEN, Cheng-Jen WANG, Tzong-yann LEE
  • Publication number: 20160340882
    Abstract: A water saving toilet device comprises a drain pipe of a basin connected with a flush unit of a toilet, thereby providing the wastewater, which is produced after the basin is used, into the flush unit of the toilet via the drain pipe to be a water for cleaning the toilet after the user used the toilet, achieving the effect of water saving.
    Type: Application
    Filed: May 21, 2015
    Publication date: November 24, 2016
    Inventor: CHIOU-YANN LEE
  • Publication number: 20160144708
    Abstract: A luggage scooter is revealed. A moveable and foldable foot rest unit is disposed on a front surface of a box. A vertical rod arranged with a handle is connected to a front end of the foot rest unit. A front wheel is set on bottom of the vertical rod while a transmission wheel is disposed on a bottom side of the box and connected to a power source. Anti-tip wheels are arranged at bottom surface of the box. The foot rest unit and the vertical rod are mounted in the box so that the luggage scooter is used as a luggage for loading objects. While being used as a scooter, the foot rest unit is extended and users sit on the box with feet stepping thereon and hands holding the handle. A drive unit drives the power source to move the transmission wheel.
    Type: Application
    Filed: May 21, 2015
    Publication date: May 26, 2016
    Inventor: CHIOU-YANN LEE
  • Patent number: 6841934
    Abstract: A white light source is obtained by converting short wavelength color light emitted from a light emitting diode (LED). The conversion is achieved by covering the LED chip with a fluorescent glue. The LED chip is mounted on a split substrate, and the outer ends of the substrate serve as terminals for the LED. A wall may be erected around the LED chip to contain the fluorescent glue, and another transparent glue may be used to cover the fluorescent glue for protection.
    Type: Grant
    Filed: February 26, 2003
    Date of Patent: January 11, 2005
    Assignee: Harvatek Corporation
    Inventors: Bily Wang, Jonnie Chuang, Yann Lee
  • Publication number: 20040164675
    Abstract: A white light source is obtained by converting short wavelength color light emitted from a light emitting diode (LED). The conversion is achieved by covering the LED chip with a fluorescent glue. The LED chip is mounted on a split substrate, and the outer ends of the substrate serve as terminals for the LED. A wall may be erected around the LED chip to contain the fluorescent glue, and another transparent glue may be used to cover the fluorescent glue for protection.
    Type: Application
    Filed: February 26, 2003
    Publication date: August 26, 2004
    Inventors: Bily Wang, Jonnie Chuang, Yann Lee
  • Patent number: 6583447
    Abstract: A surface-mount package for multiple LED chips is constructed by inscribing a groove in an insulating substrate. The LED chips are mounted in the groove and the leads are connected to metal plates, which wrap around the substrate to provide bottom contacts for surface-mounting.
    Type: Grant
    Filed: August 27, 2001
    Date of Patent: June 24, 2003
    Assignee: Harvatek Corp.
    Inventors: Bily Wang, Bill Chang, Yann Lee
  • Publication number: 20030038292
    Abstract: A surface-mount package for multiple LED chips is constructed by inscribing a groove in an insulating substrate. The LED chips are mounted in the groove and the leads are connected to metal plates, which wrap around the substrate to provide bottom contacts for surface-mounting.
    Type: Application
    Filed: August 27, 2001
    Publication date: February 27, 2003
    Inventors: Billy Wang, Bill Chang, Yann Lee
  • Publication number: 20030032212
    Abstract: An optoelectronic device is placed in a through hole of an upper substrate and mounted on a lower substrate, which is stacked under the upper substrate. The through hole forms a focusing cup for the optoelectronic device. A metallic base plate can be inserted between the optoelectronic device and the lower substrate to enhance light reflection and heat removal. The through hole can be lined with metallic coating to enhance light reflection.
    Type: Application
    Filed: August 7, 2001
    Publication date: February 13, 2003
    Inventors: Bily Wang, Bill Chang, Yann Lee
  • Publication number: 20020101252
    Abstract: A structure for being used in measuring a capacitance of a capacitor is provided. The structure includes a plurality of input terminals having an operating voltage and an operating frequency, a first quasi-inverting circuit having a first parasitic capacitor for generating a first current and electrically connected with the input terminals, a second quasi-inverting circuit having a second parasitic capacitor and a first reference capacitor for generating a second current and electrically connected with the first quasi-inverting circuit, and a third quasi-inverting circuit having the capacitor, a third parasitic capacitor and a second reference capacitor for generating a third current and electrically connected with the quasi-inverting circuit.
    Type: Application
    Filed: April 30, 2001
    Publication date: August 1, 2002
    Applicant: National Science Council
    Inventors: Huang-Chung Cheng, Gwo-Yann Lee, Cheng-Jer Yang
  • Patent number: D509195
    Type: Grant
    Filed: April 8, 2003
    Date of Patent: September 6, 2005
    Assignee: Harvatek Corporation
    Inventors: Bily Wang, Jonnie Chuang, Yann Lee