Abstract: A semiconductor device manufacturing method of forming a trench and a via in a porous low dielectric constant film formed on a substrate as an interlayer insulating film, includes: embedding a polymer having a urea bond in pores of the porous low dielectric constant film by supplying a raw material for polymerization to the porous low dielectric constant film; forming the via by etching the porous low dielectric constant film; subsequently, embedding a protective filling material made of an organic substance in the via; subsequently, forming the trench by etching the porous low dielectric constant film; subsequently, removing the protective filling material; and after the forming a trench, removing the polymer from the pores of the porous low dielectric constant film by heating the substrate to depolymerize the polymer, wherein the embedding a polymer having a urea bond in pores is performed before the forming a trench.

Abstract: In certain embodiments, a method includes forming a first etch stop layer on a first metallization layer of a semiconductor substrate. The method further includes forming, prior to forming a second metallization layer over the first metallization layer, an opening in the first etch stop layer according to a supervia mask. The method further includes forming the second metallization layer over the first metallization layer and forming a second etch stop layer on the second metallization layer. The method further includes forming, prior to forming a third metallization layer over the second metallization layer, an opening in the second etch stop layer according to the supervia mask. The method further includes forming the third metallization layer over the second metallization layer and etching a supervia opening from the third metallization layer to the first metallization layer according to the supervia mask.

Abstract: Embodiments of the invention address several issues and problems associated with etching of dielectric materials for BEOL applications. According to one embodiment, the method includes providing a patterned substrate containing a dielectric material, exposing the substrate to a gas phase plasma to functionalize a surface of the dielectric material, exposing the substrate to a silanizing reagent that reacts with the functionalized surface of the dielectric material to form a dielectric film, and sequentially repeating the exposing steps at least once to increase a thickness of the dielectric film. According to one embodiment, the dielectric material may be a porous low-k material, and the dielectric film seals the pores on a surface of the porous low-k material.

Abstract: A semiconductor device manufacturing method of forming a trench and a via in a porous low dielectric constant film formed on a substrate as an interlayer insulating film, includes: embedding a polymer having a urea bond in pores of the porous low dielectric constant film by supplying a raw material for polymerization to the porous low dielectric constant film; forming the via by etching the porous low dielectric constant film; subsequently, embedding a protective filling material made of an organic substance in the via; subsequently, forming the trench by etching the porous low dielectric constant film; subsequently, removing the protective filling material; and after the forming a trench, removing the polymer from the pores of the porous low dielectric constant film by heating the substrate to depolymerize the polymer, wherein the embedding a polymer having a urea bond in pores is performed before the forming a trench.

Abstract: A semiconductor device manufacturing method of forming a trench and a via in a porous low dielectric constant film formed on a substrate as an interlayer insulating film, includes: embedding a polymer having a urea bond in pores of the porous low dielectric constant film by supplying a raw material for polymerization to the porous low dielectric constant film; forming the via by etching the porous low dielectric constant film; subsequently, embedding a protective filling material made of an organic substance in the via; subsequently, forming the trench by etching the porous low dielectric constant film; subsequently, removing the protective filling material; and after the forming a trench, removing the polymer from the pores of the porous low dielectric constant film by heating the substrate to depolymerize the polymer, wherein the embedding a polymer having a urea bond in pores is performed before the forming a trench.

Abstract: A semiconductor device manufacturing method of forming a trench and a via in a porous low dielectric constant film formed on a substrate as an interlayer insulating film, includes: embedding a polymer having a urea bond in pores of the porous low dielectric constant film by supplying a raw material for polymerization to the porous low dielectric constant film; forming the via by etching the porous low dielectric constant film; subsequently, embedding a protective filling material made of an organic substance in the via; subsequently, forming the trench by etching the porous low dielectric constant film; subsequently, removing the protective filling material; and after the forming a trench, removing the polymer from the pores of the porous low dielectric constant film by heating the substrate to depolymerize the polymer, wherein the embedding a polymer having a urea bond in pores is performed before the forming a trench.

Abstract: Embodiments of the invention address several issues and problems associated with etching of dielectric materials for BEOL applications. According to one embodiment, the method includes providing a patterned substrate containing a dielectric material, exposing the substrate to a gas phase plasma to functionalize a surface of the dielectric material, exposing the substrate to a silanizing reagent that reacts with the functionalized surface of the dielectric material to form a dielectric film, and sequentially repeating the exposing steps at least once to increase a thickness of the dielectric film. According to one embodiment, the dielectric material may be a porous low-k material, and the dielectric film seals the pores on a surface of the porous low-k material.

Abstract: A method for treating a substrate is disclosed. The method includes forming a film stack on the substrate, the film stack comprising an underlying layer, a coating layer disposed above the underlying layer, and a patterning layer disposed above the coating layer. In the method, portions of the patterning layer are removed to form sidewalls of the patterning layer and expose portions of the coating layer, a carbon-containing layer is deposited on the exposed portions of the coating layer and non-sidewall portions of the patterning layer, and the carbon-containing layer and a portion of the coating layer are removed to expose other portions of the coating layer and the patterning layer. The method further includes repeating the deposition and removal of the carbon-coating layer at least until portions of the underlying layer are exposed.

Abstract: A method for forming a via in an integrated circuit comprises patterning a first opening in a first hardmask, the first hardmask disposed on a first organic self-planarizing polymer (OPL) layer, removing an exposed portion of the first OPL layer to define a cavity, removing an exposed portion of a second hardmask in the cavity, removing an exposed portion of a first dielectric layer disposed under the second hardmask to further define the cavity, removing an exposed portion of a first cap layer in the cavity, removing an exposed portion of a second dielectric layer to further define the cavity, removing an exposed portion of a second cap layer to further define the cavity, removing an exposed portion of a liner layer over a second conductive material in the cavity, and depositing a conductive material in the cavity.

Abstract: A method for treating a substrate is disclosed. The method includes forming a film stack on the substrate, the film stack comprising an underlying layer, a coating layer disposed above the underlying layer, and a patterning layer disposed above the coating layer. In the method, portions of the patterning layer are removed to form sidewalls of the patterning layer and expose portions of the coating layer, a carbon-containing layer is deposited on the exposed portions of the coating layer and non-sidewall portions of the patterning layer, and the carbon-containing layer and a portion of the coating layer are removed to expose other portions of the coating layer and the patterning layer. The method further includes repeating the deposition and removal of the carbon-coating layer at least until portions of the underlying layer are exposed.

Abstract: A method for etching an antireflective coating on a substrate is disclosed. The substrate comprises an organic layer, an antireflective coating layer disposed above the organic layer, and a photoresist layer disposed above the antireflective coating layer. The method includes patterning the photoresist layer to expose a non-masked portion of the antireflective coating layer and selectively depositing a carbon-containing layer on the non-masked portions of the antireflective coating layer and on non-sidewall portions of the patterned photoresist layer. The method further includes etching the film stack to remove the carbon-containing layer and to remove a partial thickness of the non-masked portions of the antireflective coating layer without reducing a thickness of the photoresist layer.

Abstract: A method for forming a via in an integrated circuit comprises patterning a first opening in a first hardmask, the first hardmask disposed on a first organic self-planarizing polymer (OPL) layer, removing an exposed portion of the first OPL layer to define a cavity, removing an exposed portion of a second hardmask in the cavity, removing an exposed portion of a first dielectric layer disposed under the second hardmask to further define the cavity, removing an exposed portion of a first cap layer in the cavity, removing an exposed portion of a second dielectric layer to further define the cavity, removing an exposed portion of a second cap layer to further define the cavity, removing an exposed portion of a liner layer over a second conductive material in the cavity, and depositing a conductive material in the cavity.

Abstract: A method for etching an antireflective coating on a substrate is disclosed. The substrate comprises an organic layer, an antireflective coating layer disposed above the organic layer, and a photoresist layer disposed above the antireflective coating layer. The method includes patterning the photoresist layer to expose a non-masked portion of the antireflective coating layer and selectively depositing a carbon-containing layer on the non-masked portions of the antireflective coating layer and on non-sidewall portions of the patterned photoresist layer. The method further includes etching the film stack to remove the carbon-containing layer and to remove a partial thickness of the non-masked portions of the antireflective coating layer without reducing a thickness of the photoresist layer.

Abstract: A method for forming a via in an integrated circuit comprises patterning a first opening in a first hardmask, the first hardmask disposed on a first organic self-planarizing polymer (OPL) layer, removing an exposed portion of the first OPL layer to define a cavity, removing an exposed portion of a second hardmask in the cavity, removing an exposed portion of a first dielectric layer disposed under the second hardmask to further define the cavity, removing an exposed portion of a first cap layer in the cavity, removing an exposed portion of a second dielectric layer to further define the cavity, removing an exposed portion of a second cap layer to further define the cavity, removing an exposed portion of a liner layer over a second conductive material in the cavity, and depositing a conductive material in the cavity.

Abstract: A method for forming a via in an integrated circuit comprises patterning a first opening in a first hardmask, the first hardmask disposed on a first organic self-planarizing polymer (OPL) layer, removing an exposed portion of the first OPL layer to define a cavity, removing an exposed portion of a second hardmask in the cavity, removing an exposed portion of a first dielectric layer disposed under the second hardmask to further define the cavity, removing an exposed portion of a first cap layer in the cavity, removing an exposed portion of a second dielectric layer to further define the cavity, removing an exposed portion of a second cap layer to further define the cavity, removing an exposed portion of a liner layer over a second conductive material in the cavity, and depositing a conductive material in the cavity.

Abstract: A method for creating one or more vias in an integrated circuit structure and the integrated circuit structure. The method includes depositing a coating layer over a hard mask layer on the integrated circuit structure; locating an initial via pattern layer over the coating layer; and etching the pattern of the one or more initial openings in the coating layer and through openings in the hard mask layer. The coating layer is a conformal deposition of an oxide, a boron nitride, or other nitride. The initial via pattern layer has one or more initial openings located therein.

Abstract: A method for profiling a film stack includes receiving a film stack having an insulation layer, a dielectric hard mask layer, and a patterned metal hard mask layer. The pattern in the patterned metal hard mask layer is transferred to the dielectric hard mask layer using a first dry etching process. The pattern in the dielectric hard mask layer is then transferred to the insulation layer using a second dry etching process including one or more halogen-containing gases. The second etching process etches the insulation layer and removes a portion of the patterned metal hard mask layer, which exposes a corner of the underlying dielectric hard mask layer. Portions of the dielectric hard mask layer that overhang the insulation layer are removed using a third dry etching process including a process composition that is more selective to the dielectric hard mask layer relative to the insulation layer.

Abstract: A method for patterning an insulation layer and selectively removing a capping layer overlying the insulation layer is described. The method utilizes a dry non-plasma removal process. The dry non-plasma removal process may include a self-limiting process.

Abstract: A method of patterning a film stack is described. The method comprises preparing a film stack on a substrate, wherein the film stack comprises a SiCOH-containing layer formed on the substrate, a silicon oxide (SiOx) layer formed on the SiCOH-containing layer, and a mask layer formed on the silicon oxide layer. A pattern is created in the mask layer. Thereafter, the pattern in the mask layer is transferred to the silicon oxide layer using a first etching process, and then the mask layer is removed. The pattern in the silicon oxide layer is transferred to the SiCOH-containing layer using a second etching process formed from a process composition comprising NF3. Thereafter, the silicon oxide layer is removed using a third etching process.

Abstract: A method for patterning an insulation layer and selectively removing a capping layer overlying the insulation layer is described. The method utilizes a dry non-plasma removal process. The dry non-plasma removal process may include a self-limiting process.