Abstract: A method for repairing a memory comprising a Memory Built-In Self Repair (MBISR) structure comprises the steps of detection of defective storage cells, and redundancy allocation. The redundancy allocation step is carried out in such a way that it combines a row and/or column oriented redundancy repair approach with a word oriented redundancy repair approach. A Memory Built-In Self Repair (MBISR) device comprises at least one memory (2) with row and/or column redundancy, at least one row and/or column Memory Built-In Self Repair (MBISR) circuit (3), and a word redundancy block (4). Furthermore, a distributed MBISR structure as well as dedicated Column/Row MBISR circuits (3) are provided.

Abstract: An integrated memory and method for testing an integrated memory is provided herein. In order to test an integrated memory having a main data memory (SP) with a plurality of data memory units, a data memory unit is addressed and input test data for testing the addressed data memory unit are applied to the main data memory (SP). The output test data are read out from the main data memory (SP) and compared with expected desired output test data in a self-test unit (STE). Deviations detected during the comparison are buffer-stored in a redundancy analysis memory (RAS). These information items buffer-stored in the redundancy analysis memory (RAS) are read out and transferred to a computing unit (RE). In the computing unit (RE), the defect positions in the output test data are identified, and a repair strategy is determined by means of redundant rows and/or redundant columns and/or redundant words provided.

Abstract: The testable read-only memory for data memory redundant logic has read-only memory units for storage of determined fault addresses of faulty data memory units. The serviceability of each read-only memory unit can be checked by application of input test data and by comparison of read output test data with expected nominal output test data.

Abstract: An interface circuit for coupling a data handling unit with a memory unit having control inputs, an address signal input, a data signal input, and a data signal output is described. The interface circuit comprises an address buffer having an input and an output, said input receiving an address signal from said data handling unit, a first multiplexer which couples said memory unit with either said output of said address buffer or with said address signal, a data buffer having an input and an output, said input receiving a data signal from said data handling unit and said output being coupled with said memory data input, a second multiplexer for selecting either said memory data signal output or said data buffer output, and a comparator for comparing said address signal with the signal from said address buffer output, generating a control signal which controls said second multiplexer.